Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Fernando Martinez Vallina"'
Publikováno v:
EIT
As FPGAs have grown ever larger, there has been a shift in the manner in which they are programmed. Early on, it was typical for designers to design all FPGA firmware in house using VHDL and Verilog. This gradually shifted towards design reuse at the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7cd9382b87136f4a129c240af262872c
https://doi.org/10.1109/eit.2017.8053393
https://doi.org/10.1109/eit.2017.8053393
Publikováno v:
EIT
Field programmable gate arrays (FPGA) are growing from the role of glue logic into the area of application acceleration and compute. This is fostered by advances in silicon technologies as well as standards based methodologies for interacting with he
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95b2e2e49bb7b01de3078d023b3cf7f3
https://doi.org/10.1109/eit.2016.7535235
https://doi.org/10.1109/eit.2016.7535235
Publikováno v:
IET Computers & Digital Techniques. 6:414-425
In this study, an image and video processing platform (IVPP) based on field programmable gate array (FPGAs) is presented. This hardware/software co-design platform has been implemented on a Xilinx Virtex-5 FPGA using a high-level synthesis and can be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05893e4d24fc90478327702864908b9c
https://doi.org/10.1049/iet-cdt.2011.0156
https://doi.org/10.1049/iet-cdt.2011.0156
Autor:
Christophe Desmouliers, Richard Hanley, Fernando Martinez Vallina, Erdal Oruklu, Semih Aslan, Jafar Saniie
Publikováno v:
Circuits and Systems. :1-9
This paper addresses the challenges of System-on-Chip designs using High-Level Synthesis (HLS). HLS tools convert algorithms designed in C into hardware modules. This approach is a practical choice for developing complex applications. Nevertheless, c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ecd94ddf36d0a2db9db65139bda0404c
https://doi.org/10.4236/cs.2012.31001
https://doi.org/10.4236/cs.2012.31001
Autor:
Jasmina Vasiljevic, Henry E. Styles, Ralph D. Wittig, Fernando Martinez Vallina, Paul Chow, Paul R. Schumacher, Jeff Fifield
Publikováno v:
FPT
In recent years, high-level languages and compilers, such as OpenCL have improved both productivity and FPGA adoption on a wider scale. One of the challenges in the design of high-performance stream FPGA applications is iterative manual optimization
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dfb5fa4c3385991d3bbc6623adf601bb
https://doi.org/10.1109/fpt.2015.7393134
https://doi.org/10.1109/fpt.2015.7393134
Publikováno v:
FPGA
FPGA devices have long been the standard for massively parallel computing fabrics with a low power footprint. Unfortunately, the complexity associated with an FPGA design has limited the rate of adoption by software application programmers. Recent ad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::03b90c5f6e0f85461271d34c1d53cdc7
https://doi.org/10.1145/2684746.2721403
https://doi.org/10.1145/2684746.2721403
Publikováno v:
IWOCL
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::091bb8adc1f2af1cce643376745a84b5
https://doi.org/10.1145/2791321.2791344
https://doi.org/10.1145/2791321.2791344
Publikováno v:
IWOCL
The introduction of Field Programmable Gate Array (FPGA) based devices for OpenCL applications provides an opportunity to develop kernels which are executed on application specific compute units which can be optimized for specific workloads such as e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::020c5586c7fb0b164fc2f6de5de60834
https://doi.org/10.1145/2791321.2791328
https://doi.org/10.1145/2791321.2791328
Publikováno v:
FPGA
Engineering complex systems inevitably requires a designer to balance many conflicting design requirements including performance, cost, power, and design time. In many cases, FPGAs enable engineers to balance these design requirements in ways not pos
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca50d5d9912b074b26ad5c597f4236a0
https://doi.org/10.1145/2435264.2435266
https://doi.org/10.1145/2435264.2435266
Publikováno v:
2007 IEEE International Conference on Electro/Information Technology.
Finite field arithmetic is essential to error correction and cryptography. Instruction set extensions are an alternative to ASICs and DSPs while providing the same performance with embedded CPUs. An instruction set extension is presented that handles
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3bf53806f0c71c1b889da91f7a40bf01
https://doi.org/10.1109/eit.2007.4374484
https://doi.org/10.1109/eit.2007.4374484