Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Felix Winterstein"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:761-774
Memory-intensive implementations often require access to an external, off-chip memory which can substantially slow down an field-programmable gate array accelerator due to memory bandwidth limitations. Buffering frequently reused data on chip is a co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e24b1d289b5f8905ea5db414cac661bc
https://doi.org/10.1109/tcad.2016.2608861
https://doi.org/10.1109/tcad.2016.2608861
Publikováno v:
FPL
High-level abstractions separate algorithm design from platform implementation, allowing programmers to focus on algorithms while building complex systems. This separation also provides system programmers and compilers an opportunity to optimize plat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::103d5788c86e110da3e4f554bd5535b9
https://doi.org/10.1145/3009971
https://doi.org/10.1145/3009971
Autor:
Felix Winterstein
This book presents novel compiler techniques, which combine a rigorous mathematical framework, novel program analyses and digital hardware design to advance current high-level synthesis tools and extend their scope beyond the industrial ‘state of t
Publikováno v:
2017 International Conference on Field-Programmable Technology
FPT
FPT
Heterogeneous CPU-FPGA systems are gaining momentum in the embedded systems sector and in the data center market. While the programming abstractions for implementing the data transfer between CPU and FPGA (and vice versa) that are available in today'
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::74b24ec7928f42a1216f97d6fb85cb32
http://hdl.handle.net/10044/1/53101
http://hdl.handle.net/10044/1/53101
Publikováno v:
FPGA
Memory systems play a key role in the performance of FPGA applications. As FPGA deployments move towards design entry points that are more serial, memory latency has become a serious design consideration. For these applications, memory network optimi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b84d9414bc743ab64fe3c7deb18cf2b
https://doi.org/10.1145/3020078.3021748
https://doi.org/10.1145/3020078.3021748
Autor:
Felix Winterstein
Publikováno v:
Separation Logic for High-level Synthesis ISBN: 9783319532219
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::501cbeb080eb26129f1c006972bed2f1
https://doi.org/10.1007/978-3-319-53222-6_6
https://doi.org/10.1007/978-3-319-53222-6_6
Autor:
Felix Winterstein
Publikováno v:
Separation Logic for High-level Synthesis ISBN: 9783319532219
FPGAs allow the implementor to tailor the interface to off-chip memory and the on-chip/off-chip memory hierarchy according to the requirements of the application. This chapter presents a high-level synthesis design aid that leverages a memory access
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8fdbb872b93b95c04add1038f29c459d
https://doi.org/10.1007/978-3-319-53222-6_5
https://doi.org/10.1007/978-3-319-53222-6_5
Autor:
Felix Winterstein
Publikováno v:
Separation Logic for High-level Synthesis ISBN: 9783319532219
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eec65b15e5c7d5b6421feb03198a457f
https://doi.org/10.1007/978-3-319-53222-6_1
https://doi.org/10.1007/978-3-319-53222-6_1
Autor:
Felix Winterstein
Publikováno v:
Separation Logic for High-level Synthesis ISBN: 9783319532219
Automatic parallelisation in high-level synthesis compilers requires a memory access and dependence analysis so as to detect parallelisation opportunities and partition the memory space accordingly. This chapter describes a static program analysis an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8912b75c0129d511bf28b95ec5010bce
https://doi.org/10.1007/978-3-319-53222-6_4
https://doi.org/10.1007/978-3-319-53222-6_4
Autor:
Felix Winterstein
Publikováno v:
Separation Logic for High-level Synthesis ISBN: 9783319532219
High-level synthesis promises significant shortening of the design cycle compared to a design entry at RTL. However, many high-level synthesis implementations require extensive code alterations to ensure synthesisability and to achieve a quality of r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66b92c16ad754563c511af8fb4d3ad0b
https://doi.org/10.1007/978-3-319-53222-6_2
https://doi.org/10.1007/978-3-319-53222-6_2