Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Fekri, Kharbash"'
Autor:
Aisha Fahad Alraeesi, Hanan Fekri Kharbash, Jawaher Saif Alghfeli, Shamma Sultan Alsaedi, Munkhjargal Gochoo
Publikováno v:
2021 IEEE International Conference on Systems, Man, and Cybernetics (SMC).
Publikováno v:
IWCMC
Paralysis is the most inhibiting among all the severe motor disabilities. Indeed, people are inflicted with paralysis as the result of an accident or a medical condition that affects - completely or partially, the way muscles and nerves function. How
Publikováno v:
The Journal of Engineering. 2018:735-744
This study compares the performance and reliability of classical complementary metal-oxide-semiconductor (CMOS) gates with Schmitt trigger (ST) ones. The ST hysteresis, caused by the added positive feedback transistors, improves the design static noi
Publikováno v:
Journal of Low Power Electronics. 10:137-148
Publikováno v:
2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO).
This paper compares classical CMOS logic gates with their Schmitt trigger (ST) versions, when sized both conventionally as well as unconventionally. The reason for studying ST logic gates is due to their positive feedback which leads to hysteresis an
Publikováno v:
2014 10th International Conference on Innovations in Information Technology (IIT).
Publikováno v:
2014 International Semiconductor Conference (CAS).
Publikováno v:
ICECS
This paper compares classical CMOS versus Schmitt trigger (ST) inverters (INVs), sized both conventionally as well as unconventionally. The reason is that ST INVs are using positive feedback (which leads to hysteresis) and are expected to exhibit muc
Publikováno v:
ICECS
This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to high
Publikováno v:
CAS 2013 (International Semiconductor Conference).
This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to oper