Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Federico Fary"'
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 11, Iss 2, p 15 (2021)
This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the
Externí odkaz:
https://doaj.org/article/748b08d7ce8c450996d752314f02cbbc
Autor:
Federico Fary, Andrea Baschirotto
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 10, Iss 4, p 35 (2020)
This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (bot
Externí odkaz:
https://doaj.org/article/cc087b8183f143f18ed877a7c5b62f9b
Autor:
Marcello De Matteis, Elia Arturo Vallicelli, Nicolas Galante, Federico Fary, Andrea Baschirotto
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:3068-3072
This brief presents a 4th-order continuous-time analog filter based on Flipped-Source-Follower stage. Source-Follower (SF) filters typically adopt pseudo-differential topology (critical for matching and bulk/substrate noise rejection) and are realize
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5c429f6b0e7c82ca2059888e6a686976
https://doi.org/10.1109/tcsii.2021.3095971
https://doi.org/10.1109/tcsii.2021.3095971
Publikováno v:
Journal of Low Power Electronics and Applications
Volume 11
Issue 2
Journal of Low Power Electronics and Applications, Vol 11, Iss 15, p 15 (2021)
Volume 11
Issue 2
Journal of Low Power Electronics and Applications, Vol 11, Iss 15, p 15 (2021)
This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::77cb29ac8201ae951afdedbd1d6c3dcf
Publikováno v:
ICECS
This paper presents a 4th-order continuous-time analog filter, with 100 MHz pass-bandwidth, based on the Super-Source-Follower biquadratic cell. The device is designed in order to meet specification for the latest telecommunications standards (LTE an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::04da271415632bb5fc1ad857441cbff5
https://doi.org/10.1109/icecs46596.2019.8964837
https://doi.org/10.1109/icecs46596.2019.8964837
Autor:
M. De Matteis, Oliver Kortner, L. Mangiagalli, Ralf P. Richter, Federico Fary, Andrea Baschirotto, A. Pipino, Hubert Kroha, F. Resta
Publikováno v:
ICECS
A Fast Tracker analog front end for small-diameter Muon Drift Tube (sMDT) detectors is hereby presented. The analog channel has been integrated in 28 nm CMOS technology and significantly improves state-of-the-art sMDT read-out systems thanks to a nov
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cbc1b0687ec5e0b7fb6758670be187ad
http://hdl.handle.net/10281/280598
http://hdl.handle.net/10281/280598
Publikováno v:
ESSCIRC
This paper presents the design in 28nm-CMOS technology of a 100MHz–3dB-bandwidth analog filter based on the Flipped-Source-Follower stage. The filter performs large inband linearity thanks to a proper local loop, whose optimization at design level
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bb191129430e9571be569e530f3f4080
http://hdl.handle.net/10281/214912
http://hdl.handle.net/10281/214912
Autor:
Federico Fary, Pierluigi Luciano, Nicolo Vladi Biesuz, Calliope Louisa Sotiropoulou, Alberto Annovi, Alberto Stabile, Luca Frontini, Matteo M. Beretta, Marcello De Matteis, Francesco Crescioli, Valentino Liberali, A. Pezzotta, Seyed Ruhollah Shojaii, Andrea Baschirotto, Saverio Citraro, Fabrizio Palla, Paola Giannetti
Publikováno v:
ICECS
In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2911dff2b9100d3f430c9a1f94e9ab01
http://hdl.handle.net/10281/123750
http://hdl.handle.net/10281/123750