DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures

Autor: Akshay Srivatsa, Mostafa Mansour, Andreas Herkersdorf, Thomas Wild, Dirk Gabriel, Sven Rheindt

Publikováno v: International Journal of Parallel Programming. 49:570-599

Embedded system applications, with their inherently limited parallelism, rarely exploit all available processing resources in large DSM-based manycore architectures. From a cache coherence perspective, this provides an opportunity to move away from g

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::33368671dbe7a0c0a7f8b410b52789a3
https://doi.org/10.1007/s10766-020-00688-6

Ghostwriter: A Cache Coherence Protocol for Error-Tolerant Applications

Autor: Natalie Enright Jerger, Joshua San Miguel, Henry Kao

Publikováno v: ICPP Workshops

Coherence induced cache misses are an important aspect limiting the scalability of shared memory parallel programs. Many coherence misses are avoidable, namely misses due to false sharing – when different threads write to different memory addresses

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e38ebc2636d5a75d1a553b7cf9d1fe09
https://doi.org/10.1145/3458744.3474045

Sentinel: Efficient Tensor Migration and Allocation on Heterogeneous Memory Systems for Deep Learning

Autor: Jiaolin Luo, Kai Wu, Hyeran Jeon, Minjia Zhang, Jie Ren, Dong Li

Publikováno v: HPCA

Memory capacity is a major bottleneck for training deep neural networks (DNN). Heterogeneous memory (HM) combining fast and slow memories provides a promising direction to increase memory capacity. However, HM imposes challenges on tensor migration a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7bdd3d9def0ebf80fbc2694642361547
https://doi.org/10.1109/hpca51647.2021.00057

TSOPER: Efficient Coherence-Based Strict Persistency

Autor: Yuan Yao, Stefanos Kaxiras, Per Ekemark, Konstantinos Sagonas, Alberto Ros

Publikováno v: DIGITUM. Depósito Digital Institucional de la Universidad de Murcia
instname
HPCA
Symposium on High Performance Computer Architecture (HPCA)
2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
DIGITUM: Depósito Digital Institucional de la Universidad de Murcia
Universidad de Murcia

We propose a novel approach for hardware-based strict TSO persistency, called TSOPER. We allow a TSO persistency model to freely coalesce values in the caches, by forming atomic groups of cachelines to be persisted. A group persist is initiated for a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9e87f1d265c1309ca756ca8c0ffcee7b
http://hdl.handle.net/10201/106146

T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware

Autor: Mark C. Jeffrey, Victor A. Ying, Daniel Sanchez

Publikováno v: ISCA

Multicores are now ubiquitous, but programmers still write sequential code. Speculative parallelization is an enticing approach to parallelize code while retaining the ease of sequential programming, making parallelism pervasive. However, prior specu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ea75237b5dfb5d388bacefcb566b9d27
https://doi.org/10.1109/isca45697.2020.00024