Výsledky vyhledávání - "Fahim Ur Rahman"

Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS

Autor: Visvesh S. Sathe, Rajesh Pamula, Fahim ur Rahman

Publikováno v: IEEE Journal of Solid-State Circuits. 55:494-504

This article describes an architecture that auto- nomously sets the operating supply voltage ( $V_{dd}$ ) of a digital system for minimum total energy dissipation, inclusive of regulator loss. The technique directly computes the energy per cycle (EPC

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::35e85c9bd6bc0193c4e17bff5af8d22c
https://doi.org/10.1109/jssc.2019.2956884

Zobrazit plný text záznamu

An All-Digital Fused PLL-Buck Architecture for 82% Average V dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Autor: Sung Kim, Xun Sun, Naveen John, Fahim ur Rahman, Xi Li, Visvesh S. Sathe, Venkata Rajesh Pamula

Publikováno v: IEEE Journal of Solid-State Circuits. 54:3215-3225

Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a r

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::eb7295c312fad9749183222fdd7ded0c
https://doi.org/10.1109/jssc.2019.2936968

Zobrazit plný text záznamu

A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation

Autor: Visvesh S. Sathe, Greg Taylor, Fahim ur Rahman

Publikováno v: IEEE Journal of Solid-State Circuits. 54:2487-2500

This paper proposes computational locking (C-lock) in all-digital phase-locked loops (PLLs) to achieve rapid frequency and phase lock acquisition. The proposed approach employs a “lock-accelerator” module that accelerates lock-times ( $T_{\mathrm

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b29c19b293682f21f5ed4dda92d2e62b
https://doi.org/10.1109/jssc.2019.2926191

Zobrazit plný text záznamu

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains

Autor: Naveen John, Rajesh Pamula, Fahim ur Rahman, Sung Kim, Roshan Kumar, Xi Li, Keith Bowman, Visvesh S. Sathe

Publikováno v: IEEE Journal of Solid-State Circuits. 54:1173-1184

Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage ( $V_{\mathrm{ dd}}$ ) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy effic

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::74405a5eb77baa53a8b339d7e48a5657
https://doi.org/10.1109/jssc.2018.2888866

Zobrazit plný text záznamu

A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction

Autor: Baosen Zhang, Fahim ur Rahman, Xun Sun, Sung Min Kim, Visvesh S. Sathe, Venkata Rajesh Pamula

Publikováno v: IEEE Solid-State Circuits Letters. 1:237-240

This letter presents a highly digital, technology scalable, and energy-efficient cryptographic-quality true random number generator (TRNG). The proposed architecture presents a balanced approach to TRNG design, relying on a simpler, noncryptographic

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::973bbfd49ae51cb0ca7eac6566ac20b7
https://doi.org/10.1109/lssc.2019.2896777

Zobrazit plný text záznamu

Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems

Autor: Visvesh S. Sathe, Fahim ur Rahman

Publikováno v: IEEE Journal of Solid-State Circuits. 53:924-935

This paper describes quasi-resonant-clocking (QRC), a continuos voltage-frequency scalable resonant clocking architecture capable of dynamic voltage and frequency scaling (DVFS). The use of runtime control by QRC is central to ensuring robust, effici

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fdd7c09d42468368ec23aee65519f793
https://doi.org/10.1109/jssc.2017.2780219

Zobrazit plný text záznamu

19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS

Autor: Akshat Boora, Rajesh Pamula, Fahim ur Rahman, Visvesh S. Sathe, Xun Sun

Publikováno v: ISSCC

Integrated circuits for ultra-low-power applications strive to minimize total system energy, while satisfying performance requirements. The supply voltage ($V_{dd}$) can be set to a Minimum Energy Point (MEP) [1, 2], where leakage and dynamic energy

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e964f8c3177724898cf0e335ce95969b
https://doi.org/10.1109/isscc.2019.8662486

Zobrazit plný text záznamu

An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS

Autor: Xun Sun, Sung Kim, Visvesh S. Sathe, Fahim ur Rahman, Baosen Zhang, V. Rajesh Pamula

Publikováno v: VLSI Circuits

We present a robust, all-digital True Random Number Generator (TRNG) architecture that efficiently combines low-quality physical random number generators (PRNGs) with integrated de-correlation and de-biasing. A 65-nm CMOS TRNG test chip demonstrates

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::caeb9116629ec25f23bd1d0df6c5f9a5
https://doi.org/10.1109/vlsic.2018.8502375

Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání