Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Fahad Bin Muslim"'
Autor:
Kashif Inayat, Fahad Bin Muslim, Javed Iqbal, Syed Agha Hassnain Mohsan, Hend Khalid Alkahtani, Samih M. Mostafa
Publikováno v:
Sensors, Vol 23, Iss 9, p 4297 (2023)
Systolic arrays are an integral part of many modern machine learning (ML) accelerators due to their efficiency in performing matrix multiplication that is a key primitive in modern ML models. Current state-of-the-art in systolic array-based accelerat
Externí odkaz:
https://doaj.org/article/08d33caba7b34af6bed254b2a03a9e9f
Publikováno v:
IEEE Access, Vol 5, Pp 2747-2762 (2017)
FPGA-based accelerators have recently evolved as strong competitors to the traditional GPU-based accelerators in modern high-performance computing systems. They offer both high computational capabilities and considerably lower energy consumption. Hig
Externí odkaz:
https://doaj.org/article/0e2d900e43654f33b6e6c1fb7fb99c96
Publikováno v:
IEEE Access, Vol 5, Pp 8419-8432 (2017)
High-level synthesis (HLS)-based design methodologies are extremely viable for industries that are sensitive to production costs. In order to have competitive advantage, the ability to have several different implementations of the same algorithm sati
Externí odkaz:
https://doaj.org/article/0e6d17dab5404794b0e302d81efe6d8f
Publikováno v:
Energies, Vol 11, Iss 3, p 542 (2018)
This paper presents line-interactive transformerless Uninterruptible Power Supply (UPS) with a fuel cell as the prime energy source. The proposed UPS consists of three major parts (i.e., an output inverter, a unidirectional DC–DC converter, and a b
Externí odkaz:
https://doaj.org/article/28b74fb4e3f9493b9ef5bfc3c19331c7
In this brief, we present FracTCAM, an efficient methodology for ternary content addressable memory (TCAM) emulation on Xilinx field-programmable gate arrays (FPGAs) by leveraging primitive architectural resources. The proposed methodology exploits t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::797229f7adfc01b064ceb94aa845949f
Publikováno v:
Arabian Journal for Science and Engineering. 47:3847-3860
This paper formulates a new strategy for designing a robust anti-windup (AW) controller for nonlinear delayed system with parametric uncertainties, time delays, input nonlinearity, and exogenous perturbations. A novel robust decoupling framework is d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b416c57279d908acf7c62a2dc6b55230
https://doi.org/10.1007/s13369-021-06095-4
https://doi.org/10.1007/s13369-021-06095-4
Autor:
Arsalan Ali Malik, Nasim Ullah, Anees Ullah, Bushra Sultana, Pedro Reviriego, Fahad Bin Muslim, Ali Zahir, Waleed Ahmad
Publikováno v:
Electronics, Vol 10, Iss 899, p 899 (2021)
e-Archivo. Repositorio Institucional de la Universidad Carlos III de Madrid
instname
Electronics
Volume 10
Issue 8
e-Archivo. Repositorio Institucional de la Universidad Carlos III de Madrid
instname
Electronics
Volume 10
Issue 8
This article belongs to the Special Issue Architecture and CAD for Field-Programmable Gate Arrays (FPGAs) Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cdf3a6571deb6098627b893b0be0d0a2
https://hdl.handle.net/10016/33501
https://hdl.handle.net/10016/33501
Publikováno v:
IEEE Access, Vol 5, Pp 8419-8432 (2017)
High-level synthesis (HLS)-based design methodologies are extremely viable for industries that are sensitive to production costs. In order to have competitive advantage, the ability to have several different implementations of the same algorithm sati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2372ed0b88e2a7056e86c9dfc91dac33
https://ieeexplore.ieee.org/document/7769188/
https://ieeexplore.ieee.org/document/7769188/
Publikováno v:
International Journal of Internet Technology and Secured Transactions. 11:241
Time synchronisation in any distributed network can be achieved by using application layer protocols for time correction. Time synchronisation method proposed in this article uses symbol timing recovery at the physical layer to correct the applicatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3ab6e3e13c328efa90b6f7932007d4de
https://doi.org/10.1504/ijitst.2021.114928
https://doi.org/10.1504/ijitst.2021.114928
Autor:
Arsalan Ahmad Raja, Fahad Bin Muslim, Muhammad Aamir, Azhar Ul-Haq, Marium Jalal, Carlo Cecati, Javed Iqbal
Publikováno v:
Computers & Electrical Engineering. 88:106885
This paper presents an extensive simulation-based and experimental validation of One-Cycle Control (OCC) over a nine-level power inverter using Cyclone III FPGA from Intel. OCC is a technique that exploits the nonlinear nature of multilevel power con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::898ddc7778ab9090d1ccde8e2ee31df4
https://doi.org/10.1016/j.compeleceng.2020.106885
https://doi.org/10.1016/j.compeleceng.2020.106885