Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Fabio G. Rossato G. da Silva"'
Publikováno v:
ICECS
This work investigates the Mirror full adder circuit using a 7nm FinFET technology, considering the SET susceptibility and the robustness of all internal nodes of the circuit. This work aims to identify how this full adder topology behaves in a speci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6a0e983f1e02e7b48ab6a56e99e4c4d
https://doi.org/10.1109/icecs49266.2020.9294891
https://doi.org/10.1109/icecs49266.2020.9294891
Publikováno v:
MWSCAS
To mitigate variability effects, this work explores decoupling cells on different adder topologies using a 7nm FinFET technology. Process variability shows an impact of up to 20% on nominal voltage and superior to 50% at near-threshold operation. Aft
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b12eabe5c9ba871df652854ea33b80cb
https://doi.org/10.1109/mwscas48704.2020.9184613
https://doi.org/10.1109/mwscas48704.2020.9184613
Autor:
Cleiton Magano Marques, Roberto B. Almeida, Paulo F. Butzen, Ricardo Reis, Fabio G. Rossato G. da Silva, Cristina Meinhardt
Publikováno v:
Microelectronics Reliability. :196-202
The semiconductor industry is exploring technology scaling to pursuit the Moore's Law. The actual processors operation frequency grows the need for fast memories. Nowadays, SRAM cells occupy a considerable area in VLSI designs. Several challenges fol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49a65aaf5df7d23879bac01956dce4b5
https://doi.org/10.1016/j.microrel.2018.07.134
https://doi.org/10.1016/j.microrel.2018.07.134
Publikováno v:
ICECS
Near threshold operation reaches good results to energy critical applications. However, it introduces a considerable degradation on delay. Moreover, considering nano-effects, circuits operating at near-threshold are more sensitive to process variabil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c15465e9c9c6a87beb6a3367251d86e
https://doi.org/10.1109/icecs46596.2019.8965022
https://doi.org/10.1109/icecs46596.2019.8965022
Publikováno v:
ICECS
This paper evaluates ten different XOR logic gates arrangements behavior at near-threshold operation under process, voltage, and temperature (PVT) variability effects. The experiments adopt the 7nm FinFET High Performance and Low Standby Power techno
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f13f9f7fa59ca6cfcb02b0e18b27d78
https://doi.org/10.1109/icecs.2018.8618065
https://doi.org/10.1109/icecs.2018.8618065
Publikováno v:
ICECS
This work compares many different transistors arrangements of XOR logic gates under PVT variability effect in 16nm device technologies: CMOS Bulk and FinFET. The objective is to identify how these two different device technologies deal with PVT varia
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::310e1fe344e536b5eeac86d45052647d
https://doi.org/10.1109/icecs.2016.7841255
https://doi.org/10.1109/icecs.2016.7841255