Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Fabian Schuiki"'
Publikováno v:
IEEE Transactions on Computers, 70 (11)
Data-parallel applications, such as data analytics, machine learning, and scientific computing, are placing an ever-growing demand on floating-point operations per second on emerging systems. With increasing integration density, the quest for energy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0b38c0406d715d271a06ace0a88b1cbd
https://doi.org/10.1109/tc.2020.3027900
https://doi.org/10.1109/tc.2020.3027900
Autor:
Thomas Benz, Frank K. Gurkaynak, Fabian Schuiki, Florian Zaruba, Luca Bertaccini, Luca Benini
Publikováno v:
ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC)
ESSCIRC
ESSCIRC
We present Thestral, a 10-core RISC-V chip for energy-proportional parallel computing manufactured in 22 nm FD-SOI technology. Thestral contains a control core and a nine-core compute cluster. Each core features a single-precision floating-point unit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bc5f29d99db544d1317d5b4c312a3ff9
http://hdl.handle.net/11585/871055
http://hdl.handle.net/11585/871055
Publikováno v:
IEEE Transactions on Computers, 70 (2)
IEEE Transactions on Computers, 70 (2)
ISSN:0018-9340
ISSN:1557-9956
ISSN:0018-9340
ISSN:1557-9956
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1159098b5b8fe2fe6edf4c0889abd2de
http://hdl.handle.net/11585/792005
http://hdl.handle.net/11585/792005
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29 (4)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29 (4)
The slowdown of Moore's law and the power wall necessitates a shift toward finely tunable precision (a.k.a. transprecision) computing to reduce energy footprint. Hence, we need circuits capable of performing floating-point operations on a wide range
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ec15221b47a0cde5a000578e9357f48f
Publikováno v:
DATE
Sparse-dense linear algebra is crucial in many domains, but challenging to handle efficiently on CPUs, GPUs, and accelerators alike; multiplications with sparse formats like CSR and CSF require indirect memory lookups. In this work, we enhance a memo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7d777343de598f907f7b3e9c3f0bc954
http://arxiv.org/abs/2011.08070
http://arxiv.org/abs/2011.08070
Publikováno v:
ISCAS
To provide high computational capabilities, and, at the same time, minimize the power consumption, modern Systems-on-Chip (SoCs) target very low energy consumption per operation as a primary objective. This goal has been achieved in recent years by a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a7eb037612cab2e4012f3c8b7dfcf417
https://doi.org/10.1109/iscas45731.2020.9180961
https://doi.org/10.1109/iscas45731.2020.9180961
Publikováno v:
Hot Chips Symposium
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2c6ed6353a871f0432f6abcd20c2cfae
https://doi.org/10.1109/hcs49909.2020.9220474
https://doi.org/10.1109/hcs49909.2020.9220474
Publikováno v:
PLDI
Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDL are, due to their sheer complexity, insufficient to transport designs through modern circuit design flows. Instead, each design automation tool lowers HDLs to its own Intermed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9eadcf429b55ffc79edc914b13ac687c
http://arxiv.org/abs/2004.03494
http://arxiv.org/abs/2004.03494
Autor:
Fabian Schuiki, A. Cristiano I. Malossi, Germain Haugou, Frank K. Gurkaynak, Michael Schaffner, Florian Scheidegger, Luca Benini, Christoph Hagleitner, Stefan Mach, Dionysios Diamantopoulos
Publikováno v:
COOL CHIPS
2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
The performance improvement rate of conventional von Neumann processors has slowed as Moore's Law grinds to an economic halt, giving rise to a new age of heterogeneity for energy-efficient computing. Extending processors with finely tunable precision
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::193f945349c6af87d81ffa15f0dd1753
https://doi.org/10.1109/coolchips49199.2020.9097644
https://doi.org/10.1109/coolchips49199.2020.9097644
Publikováno v:
CF
In heterogeneous computer architectures, the serial part of an application is coupled with domain-specific accelerators that promise high computing throughput and efficiency across a wide range of applications. In such systems, the serial part of a p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::51bb5256222917f3302196c9b00701ea
http://hdl.handle.net/11585/798347
http://hdl.handle.net/11585/798347