Výsledky vyhledávání - "FPGA prototype"

Akademický článek

Superior Implementation of Accelerated QR Decomposition for Ultrasound Imaging

Autor: S. G. Sreejeesh, R. Sakthivel, Jayaraj U. Kidav

Publikováno v: IEEE Access, Vol 8, Pp 156244-156260 (2020)

In this work, a novel Minimum Variance Distortion less Response (MVDR) beamformer architecture in which the adaptive weight vector is computed based on modified Column wise Givens Rotation (CGR) is presented. As compared to the conventional MVDR beam

Externí odkaz: https://doaj.org/article/fa6885984b984a7189eab8c138988940

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Akademický článek

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Akademický článek

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A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning

Autor: Nanjian Wu, Ying Wang, Zhen He, Liyuan Liu, Tengxiao Wang, Gang Luo, Ping Li, Cong Shi, Min Tian, Xichuan Zhou

Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 69:1657-1661

For embedded, mobile and edge-computing intelligent applications, this brief proposes a low-cost real-time neuromorphic hardware system of spiking Extreme Learning Machine (ELM) equipped with on-chip triplet-based reward-modulated spike-timing-depend

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f6d24af3e598b2e6852aeda37cc61b5f
https://doi.org/10.1109/tcsii.2021.3117699

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FPGA-Based Implementation of an Event-Driven Spiking Multi-Kernel Convolution Architecture

Autor: Yuechao Wang, Wei Shi, Guohe Zhang, Jian Zhang, Lichen Feng, Tengbo Wang

Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 69:1682-1686

This brief presents an event-driven spiking multi-kernel convolution architecture for processing address-event representation (AER) streams from dynamic vision sensor (DVS) chips. The processor architecture is designed based on leaky integrate-and-fi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::aca4514659d9df02be7213d78e058026
https://doi.org/10.1109/tcsii.2021.3126012

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A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages

Autor: Shan Shen, Tianxiang Shao, Qingde Lin, Ming Ling, Jun Yang, Ke Tan

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:2197-2209

To improve the performance of SRAM in caches under near-threshold voltages, several timing speculation techniques, such as the cross-sensing SRAM (CS-SRAM), are proposed. Meanwhile, for a given process, voltage, and temperature (PVT) condition, CS-SR

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::18d9e56ce2124734968f3ebe3e5625eb
https://doi.org/10.1109/tvlsi.2021.3120653

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An attack-immune trusted architecture for supervisory aircraft hardware

Autor: Chi Zhang, Mai Xu, Zhenyu Guan, Dawei Li, Jianwei Liu, Dongxu Cheng, Wei Zhao

Publikováno v: Chinese Journal of Aeronautics. 34:169-181

With the wide application of electronic hardware in aircraft such as air-to-ground communication, satellite communication, positioning system and so on, aircraft hardware is facing great secure pressure. Focusing on the secure problem of aircraft har

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2f0aff8698a47de1c55ba994ceffd930
https://doi.org/10.1016/j.cja.2021.03.004

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Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR

Autor: Joshua Roy Palathinkal, Sudip Ghosh, Yuvam Bhateja, Hafizur Rahaman

Publikováno v: Circuits, Systems, and Signal Processing. 41:867-891

In this article, an FPGA-based hardware prototype design has been proposed and implemented in real time for the security of the Electronic Patient Medical Record. This proposed hardware can be integrated into various medical image scanning instrument

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::07e21f3849a423accea979a000068131
https://doi.org/10.1007/s00034-021-01807-5

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Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype

Autor: Dina Kamel, Clément Hoffmann, Hanlin Liu, Yu Yu, Davide Bellizia, François-Xavier Standaert, Pierrick Méaux

Publikováno v: IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2021, no.3, p. 390-417 (2021)
Transactions on Cryptographic Hardware and Embedded Systems, Vol 2021, Iss 3 (2021)

Hard learning problems are important building blocks for the design of various cryptographic functionalities such as authentication protocols and post-quantum public key encryption. The standard implementations of such schemes add some controlled err

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8aa791f85a4d302348980efb81d61168
https://doi.org/10.46586/tches.v2021.i3.390-417

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