Zobrazeno 1 - 10
of 83
pro vyhledávání: '"F. de Crecy"'
Publikováno v:
Journal of Electronic Materials. 43:685-694
Chip-to-wafer stacking is a key enabling technology for two and half dimension (2.5D) as well as for three dimension (3D), with technological challenges driven by the increase of the die surface and the number of input/outputs (I/Os) and the reductio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0072ea4bfa0209bdf1b7a5515d25cc30
https://doi.org/10.1007/s11664-013-2710-0
https://doi.org/10.1007/s11664-013-2710-0
Autor:
F. Schnegg, C. Karoui, G. Klug, Gilles Simon, H. Luesebrink, R. Anciant, K. Martinschitz, A. Attard, G. Parès, F. De Crecy, A. N'hari, D. Cruau
Publikováno v:
International Symposium on Microelectronics. 2012:000710-000719
Chip-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by on one hand the increase of the die surface and the number of I/Os and on the other hand by the reduction of the vertical dimension
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea5801701485e2ebc0d7025c4b12e415
https://doi.org/10.4071/isom-2012-wa61
https://doi.org/10.4071/isom-2012-wa61
An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization
Autor:
L. Di Cioccio, Didier Landru, F. De Crecy, Rachid Taibi, Gweltaz Gaudin, Pierric Gueguen, L.L. Chapelon, Laurent Clavelier, François Rieutord, Ionut Radu, Cedrick Chappaz
Publikováno v:
Journal of The Electrochemical Society. 158:P81-P86
An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed42875d0c37a88452ac1bd138b1c6d1
https://doi.org/10.1149/1.3577596
https://doi.org/10.1149/1.3577596
Autor:
G. Parès, J. Mazuir, F. de Crecy, N. Sillon, L.L. Chapelon, Stephane Moreau, András Borbély, C. Maurice
Publikováno v:
Scopus-Elsevier
Through Silicon Via (TSV) is a key enabling technology for 3D stacking. One of the main concerns regarding the TSV introduction inside the IC fabrication is the resulting stress build up in the silicon substrate that may induce warpage or expansion a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::63571d59e5e8547204f31d10e091c682
https://doi.org/10.4071/isom-2011-tp6-paper1
https://doi.org/10.4071/isom-2011-tp6-paper1
Autor:
Ionut Radu, L.L. Chapelon, Francois Rieutord, Lea Di Cioccio, P. Gueguen, Gweltaz Gaudin, Laurent Clavelier, F. De Crecy, Cedrick Chappaz, Rachid Taibi, Didier Landru
Publikováno v:
ECS Transactions. 33:3-16
Bonding is one of the key stages for 3D integration with thinning and trough silicon via. It has to respect some global constraints for these devices. For example, a low temperature process is required when the bonding is done after or during the bac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7253c837e1bbaa4004d6932345edc4a5
https://doi.org/10.1149/1.3483489
https://doi.org/10.1149/1.3483489
Publikováno v:
Microelectronics Reliability. 47:769-772
An extraction method to determine the permittivity of ultra low k (ULK) dielectrics on real integrated structures is presented. It is a two-step method based on a comparison between measured and simulated capacitance. A best-estimate value of the k U
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8cdabbd95388b1f20be29c9a4744ca22
https://doi.org/10.1016/j.microrel.2007.01.057
https://doi.org/10.1016/j.microrel.2007.01.057
Autor:
J. Piquet, Alexis Farcy, B. Blampey, Cedric Bermond, Joaquim Torres, Thierry Lacrevaz, T.T. Vo, G. Angenieux, Mickael Gros-Jean, O. Cueto, F. de Crecy, Bernard Flechet
Publikováno v:
Microelectronic Engineering. 83:2184-2188
High permittivity insulators (High-K) are progressively introduced in high-speed integrated passives and devices in order to optimize circuits performances. However, High-K properties are expected to vary with manufacturing process and also frequency
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8178a1810928e38626f9e41b6dbd6c6a
https://doi.org/10.1016/j.mee.2006.10.030
https://doi.org/10.1016/j.mee.2006.10.030
Publikováno v:
Journal of Computational Electronics. 5:171-175
In the last years, different techniques have been proposed to include quantization effects in simulation of electron transport in nanoscale devices. The Effective Potential approach has been demonstrated as a possible correction method for describing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ed25f4329b23f4b88b62e19449a5a98
https://doi.org/10.1007/s10825-006-8839-9
https://doi.org/10.1007/s10825-006-8839-9
Autor:
F. de Crecy, Papa Momar Souare, J. Pruvost, Clement Tavernier, Perceval Coudrain, S. Dumas, Bastien Giraud, Alexis Farcy, H. Ben-Jamaa, Jean Michailos, N. Hotellier, L. Le Pailleur, András Borbély, C. Chancel, J.-M. Riviere, R. Franiatte, Sebastien Gallois-Garreignot, Vincent Fiori, C. Laviron, Jean-Philippe Colonna, Severine Cheramy
Publikováno v:
2014 IEEE International Electron Devices Meeting.
We present an advanced and comprehensive platform for thermal dissipation studies in TSV-based 3D ICs. A 2-tier 3D test chip with through silicon via (TSV) and μ-bump is used for thermal characterization with unprecedented precision and design explo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::97a14ba8c0911fe1c139fec8cca2e7cc
https://doi.org/10.1109/iedm.2014.7047175
https://doi.org/10.1109/iedm.2014.7047175
Autor:
Yvan Avenas, Perceval Coudrain, G. Belly, Jean-Philippe Colonna, Severine Cheramy, F. de Crecy, R. Prieto
Publikováno v:
International Workshop on Thermal Investigations of IC´S and Systems (THERMINIC 2014)
International Workshop on Thermal Investigations of IC´S and Systems (THERMINIC 2014), Sep 2014, Londres, United Kingdom
International Workshop on Thermal Investigations of IC´S and Systems (THERMINIC 2014), Sep 2014, Londres, United Kingdom
Heat generation in integrated circuits has become in few decades one of the most limiting factors for performance improvement in mobile device components, such as cell phones or tablets. In these devices, heat dissipation is limited to a few Watts as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6e2164b88c6313dfd665826e68d6ac77
https://hal.archives-ouvertes.fr/hal-01084456
https://hal.archives-ouvertes.fr/hal-01084456
