Zobrazeno 1 - 4
of 4
pro vyhledávání: '"F. Z. Ieromnimon"'
Autor:
S. Blionas, L. Bisdounis, D. E. Metafas, Roberto Zafalon, E. Macii, P. Rouzet, C. Dre, A. Tatsaki, Luca Benini, F. Z. Ieromnimon
The authors present the architecture of a low-power system-on-chip (SoC) that implements baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. The design is based on the HIPERLAN/2
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::50514d8eb6f69ee2e4550bf79e44724a
http://hdl.handle.net/11583/1402080
http://hdl.handle.net/11583/1402080
Publikováno v:
MASCOTS
We present a case study of the use of a Unix/C/Verilog production environment to aid the design, from concept to physical prototype, of the PACE parallel graph rewriting architecture. The entire architecture has been modelled, so that simulated runs
Publikováno v:
PDP
The PACE architecture is an extensible, distributed memory multiprocessor that is designed specifically to support the graph reduction model of computation. PACE differs from most other research projects in this area in that it advocates the use of a
Autor:
S. Blionas, A. Tatsaki, D. E. Metafas, T. Trimis, C. Dre, A. Pneymatikakis, Kostas Masselos, F. Z. Ieromnimon, C. Drosos, T. Pagonis, A. Vontzalidis
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540441083
FPL
FPL
In this paper the design of a partly reconfigurable System-on-Chip (SoC) for wireless LANs is described. The reconfigurable System-on-Chip will realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The initial version of the system will incl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e7f198c2466f1b32280a002735905dd
https://doi.org/10.1007/3-540-46117-5_112
https://doi.org/10.1007/3-540-46117-5_112