Výsledky vyhledávání - "F. Tcheme Wakam"

Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterization for 1T-DRAM applications

Autor: X. Mescot, F. Tcheme Wakam, C. Vizioz, F. Aussenac, J.M. Hartmann, Kyung Hwa Lee, Joris Lacord, M. Bawedin, L. Brevard, Pascal Besson, Zdenek Chalupa, Virginie Loup

Publikováno v: 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS).

A2RAM devices are fabricated using an adaptation of Si-Nanowire process flow. They include a Si-SiGe heterostructure to improve memory performance. Even the device structure is not exactly what we expect, we succeed to evidence 1T-DRAM programming.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3d0be30c878ea61bbaac30aefc29fc6b
https://doi.org/10.1109/eurosoi-ulis53016.2021.9560676

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Si/Si0.7Ge0.3 A2RAM nanowires fabrication and characterization for 1T-DRAM applications

Autor: J. Lacord, F. Tcheme Wakam, Z. Chalupa, J.-M. Hartmann, P. Besson, V. Loup, C. Vizioz, L. Brevard, F. Aussenac, X. Mescot, K. Lee, M. Bawedin

Publikováno v: Solid-State Electronics. 193:108294

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7e6d72453949fa662f5d50ac49cac541
https://doi.org/10.1016/j.sse.2022.108294

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A2RAM Compact Modeling: From DC to 1T-DRAM Memory Operation

Autor: F. Tcheme Wakam, Gerard Ghibaudo, Sorin Cristoloveanu, M. Bawedin, Joris Lacord, J.-Ch. Barbe, Sebastien Martinie

Publikováno v: Solid-State Electronics
Solid-State Electronics, Elsevier, 2019, pp.107732. ⟨10.1016/j.sse.2019.107732⟩
Solid-State Electronics, Elsevier, 2020, 168, pp.107731. ⟨10.1016/j.sse.2019.107731⟩

In this work, we present a compact modeling of capacitorless A2RAM memory cell. It is obtained by combining A2RAM DC compact model with an equivalent circuit that mimics the memory state. The DC modeling is achieved by considering the A2RAM architect

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::073fa69ed57bb13cc0ca748500df9b5f
https://hal.archives-ouvertes.fr/hal-02380158

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Pure boron monolayer to boost A2RAM performance

Autor: F. Tcheme Wakam, M. Bawedin, Joris Lacord, Sorin Cristoloveanu, Thierry Poiroux, Sebastien Martinie

Publikováno v: 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

We propose a proof-of-concept A2RAM memory built with a pure boron monolayer bridge used as performance booster. The study is based on TCAD simulations and the results are compared to the ones obtained on standard A2RAM cell.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0a6a2841e5ddd827a34001ae0fa6f66f
https://doi.org/10.1109/eurosoi-ulis45800.2019.9041878

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Modeling of the bridge threshold voltage in A2RAM cell

Autor: Sebastien Martinie, M. Bawedin, F. Tcheme Wakam, Thierry Poiroux, Joris Lacord, Sorin Cristoloveanu

Publikováno v: 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

We propose an analytical model of the bridge threshold voltage that governs the operation of the A2RAM capacitorless memory. It was developed starting from the solution of 1D Poisson equation in the unusual A2RAM vertical stack, and it was validated

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b372801e123f29a30493a76d3cb09478
https://doi.org/10.1109/eurosoi-ulis45800.2019.9041917

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Doping profile extraction in thin SOI films: application to A2RAM

Autor: Maryline Bawedin, S. Cristoloveanu, F. Tcheme Wakam, Sebastien Martinie, J.-Ch. Barbe, Gerard Ghibaudo, Joris Lacord

Publikováno v: EuroSOI-ULIS 2018
EuroSOI-ULIS 2018, Mar 2018, Granada, Spain
Solid-State Electronics
Solid-State Electronics, Elsevier, 2019, 159, pp.3-11. ⟨10.1016/j.sse.2019.03.038⟩
2018 EUROSOI-ULIS Proceedings
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Mar 2018, Granada, Spain. pp.1-4, ⟨10.1109/ULIS.2018.8354339⟩
Solid-State Electronics, 2019, 159, pp.3-11. ⟨10.1016/j.sse.2019.03.038⟩
HAL

session 1: Fabrication and Process characterization; International audience; We propose for the first time a method based on C-V measurement to extract the bridge doping profile which governs the A2RAM performances. Assessed with TCAD simulation and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a578c67814303936f889e5d5f31d147c
https://hal-cea.archives-ouvertes.fr/cea-02270895

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Optimization guidelines of A2RAM cell performance through TCAD simulations

Autor: F. Tcheme Wakam, J. Lacord, S. Martinie, J.-Ch. Barbe, M. Bawedin, S. Cristoloveanu

Publikováno v: 2017 SISPAD Proceedings
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2017, Kamakura, Japan. pp.329-332, ⟨10.23919/SISPAD.2017.8085331⟩

session: Future Devices (12.4); International audience; A2RAM belongs to the 1T-DRAM family and is a potential candidate to replace the traditional 1T/1C- DRAM [1-2]. In this paper, we propose a TCAD simulation [3] methodology to assess A2RAM perform

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8b74f7daca0035e2389e9823404da15a
https://hal.archives-ouvertes.fr/hal-02007238

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