Zobrazeno 1 - 10
of 60
pro vyhledávání: '"F. Pintchovski"'
Autor:
F. Pintchovski, J. P. Stark, J. O. Olowolafe, C. C. Lee, D. Jawarani, Hisao Kawasaki, J. Klein
Publikováno v:
Journal of The Electrochemical Society. 141:302-306
Intermetallic compound formation in Ti/Al alloy and TiN/Al alloy thin-film couples has a strong influence on the electromigration lifetime of Al alloy interconnects used in integrated circuits. The morphologies and types of this compound are investig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::987da8c8f16d0e6e551fbfb9959eb94f
https://doi.org/10.1149/1.2054705
https://doi.org/10.1149/1.2054705
Autor:
R. Bertram, P.G.Y. Tsui, B. Pappert, F. Pintchovski, S.W. Sun, J.R. Yeargain, Jeffrey L. Klein, B.M. Somero
Publikováno v:
IEEE Transactions on Electron Devices. 39:2733-2739
A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5- mu m microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94de5c33112929fa47621bb181c47a88
https://doi.org/10.1109/16.168754
https://doi.org/10.1109/16.168754
Autor:
Horacio Mendez, Robert E. Jones, S.A. Ernst, Yee-Chaung See, Jeffrey L. Klein, T.C. Mele, Frank K. Baker, Richard D. Sivan, Wayne M. Paulson, E.O. Travis, James D. Hayden, James R. Pfiester, Bich-Yen Nguyen, B.M. Somero, T. McNelly, F. Pintchovski, M. Lien, Louis C. Parrillo
Publikováno v:
IEEE Transactions on Electron Devices. 38:876-886
An advanced, high-performance, half-micrometer generation technology has been developed for fast CMOS SRAM circuits. This process features an aggressive interwell isolation module which allows scaling of the n/sup +/ to p/sup +/ space to less than 2
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::17d827c3ec3ab0333700be96c635b9cd
https://doi.org/10.1109/16.75218
https://doi.org/10.1109/16.75218
Autor:
R. Marsh, R. Venkatraman, R. Mosely, Roc Blumenthal, P. Zhang, Robert W. Fiordalice, T. Sparks, J. Farkas, H. Zhang, Dharmesh Jawarani, J. Klein, T. Guo, F. Pintchovski, Hisao Kawasaki, T. P. Ong, Elizabeth Weitzman, Wei Wu, Ajay Jain, Martin Gall, S. Garcia, M. Fernandes
Publikováno v:
Applied Physics Letters. 73:82-84
This letter reports an investigation of two unique dual inlaid metallization approaches with low pressure chemical vapor deposition (LPCVD) of aluminum (Al) for sub-0.35 μm ultra-large-scale-integration interconnect technology: (1) warm Al/CVD Al/co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::598a6557796787745badfd86ba5d3d2b
https://doi.org/10.1063/1.121731
https://doi.org/10.1063/1.121731
Autor:
E. Travis, F. Pintchovski, C. Chen, R. Dillard, Jeffrey L. Klein, B. Boeck, M. Woo, S. Koenigseder, P. Manos
Publikováno v:
Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference.
A novel triple-level-metal process, utilizing tungsten for first-level metallization, has been developed for use in submicron arrays. The contact barrier is a composite layer of sputtered and CVD TiN, providing for good adhesion of the blanket tungst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b3143a5a606c337ebba943c74a6bb22
https://doi.org/10.1109/vmic.1989.78074
https://doi.org/10.1109/vmic.1989.78074
Publikováno v:
Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference.
Summary form only given. Polysilicon plug technology takes advantage of the desirable properties of LPCVD polysilicon (i.e. conformal step coverage, smooth texture, good etchability) to planarize submicron contacts. In addition, sputtered and CVD bar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0553cee08e31c3221be732b70a2a79f8
https://doi.org/10.1109/vmic.1989.78048
https://doi.org/10.1109/vmic.1989.78048
Publikováno v:
Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference.
The electromigration resistance for the Al-Cu-Si alloy/titanium nitride/titanium silicide barrier contact system was evaluated as a function of the deposited Ti thickness (0-1000 AA). Both the conventional constant current stress and current ramping
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35bf95af01a14571564a4c4868c61b16
https://doi.org/10.1109/vmic.1989.78035
https://doi.org/10.1109/vmic.1989.78035
Autor:
T. McNelly, S.A. Ernst, James D. Hayden, T.C. Mele, Frank K. Baker, Richard D. Sivan, B.M. Somero, Bich-Yen Nguyen, Wayne M. Paulson, M. Lien, James R. Pfiester, E.O. Travis, Louis C. Parrillo, F. Pintchovski, Jeffrey L. Klein, B. Jones, Horacio Mendez, Yee-Chaung See
Publikováno v:
International Technical Digest on Electron Devices Meeting.
An advanced high-performance sub-half-micron technology for fast CMOS SRAMs (static RAMs) has been developed. Features of this thin-well process include: an aggressive interwell isolation module, framed-mask poly-buffered LOCOS isolation (FMPBL), a 1
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::47332023cd41494ebeb77a2f92bad57e
https://doi.org/10.1109/iedm.1989.74311
https://doi.org/10.1109/iedm.1989.74311
Autor:
Kuo-Tung Chang, P. Manos, J. Klein, B. Smith, S. Lai, R. Dillard, E. Travis, F. Pintchovski, M. Woo
Publikováno v:
International Symposium on VLSI Technology, Systems and Applications.
A 0.8- mu m CMOS (complementary metal-oxide-semiconductor) triple-level-metal ASIC (application-specific integrated circuit) technology has been developed. Features of this process include heavy twin-well architecture, improved LOCOS (local oxidation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb967fb20800d3238fbb38af27ea0256
https://doi.org/10.1109/vtsa.1989.68614
https://doi.org/10.1109/vtsa.1989.68614
Autor:
K. Baker, D. Tang, J. Klein, F. Pintchovski, J. Schmiesing, C.S. Meyer, Kuo-Tung Chang, D. Hoang, S. Lai
Publikováno v:
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.
An advanced triple-level metal CMOS technology (TRIM), which uses a twin-well approach to achieve optimal device performance, is described in detail with emphasis on novel process like borophosphosilicate glass wet/dry etch, barrier metal, and boron-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::389b5a79a26bbdb7d213e531261a1c3a
https://doi.org/10.1109/cicc.1988.20932
https://doi.org/10.1109/cicc.1988.20932