High performance CMOS FDSOI devices activated at low temperature

Autor: Louis Hutin, J. Mazurier, D. Barge, L. Pasini, Olivier Weber, Frédéric Mazen, F. Piegas Luce, Claire Fenouillet-Beranger, M. Vinet, Antoine Cros, E. Ghegin, B. Mathieu, S. Chhun, J. Borrel, Frederic Boeuf, Quentin Rafhay, Anthony Payet, Michel Haond, Perrine Batude, M. Casse, Fuccio Cristiano, Benoit Sklenard, Zineb Saghi, Joris Lacord, D. Blachier, J.P. Barnes, Gerard Ghibaudo, Francois Andrieu, V. Mazzocchi, N. Rambal, J. Micout, Vincent Delaye, V. Lapras, Laurent Brunet, R. Daubriac, Pascal Besson

Publikováno v: Proceedings of the 2016 IEEE Symposium on VLSI Technology
2016 IEEE Symposium on VLSI Technology
2016 IEEE Symposium on VLSI Technology, Jun 2016, Honolulu, United States. ⟨10.1109/VLSIT.2016.7573407⟩

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::733572509907569cf7c31dbc0cecdb89
https://hal.laas.fr/hal-01730659

High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator

Autor: M. Vinet, Michel Haond, Claire Fenouillet-Beranger, O. Rozeau, F. Allain, Louis Hutin, Sebastien Kerdiles, B. Mathieu, F. Piegas Luce, Pascal Besson, Shay Reboh, Laurent Brunet, Gerard Ghibaudo, Benoit Sklenard, L. Pasini, M. Casse, N. Rambal, Claude Tabone, D. Lafond, F. Aussenac, Perrine Batude, G. Audoit, S. Martini, Nicolas Bernier, J.M. Hartmann, G. Romano, S. Barraud, V. Barral

Publikováno v: 2015 VLSI-Technology Technical Digest
2015 IEEE Symposium on VLSI Technology
2015 IEEE Symposium on VLSI Technology, Jun 2015, Kyoto, Japan. pp.T50-T51, ⟨10.1109/VLSIT.2015.7223699⟩

session 5: 3D Systems and Packaging; International audience; 3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performan

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::37bd105e2413a9ec146cc1437fd30489
https://hal.archives-ouvertes.fr/hal-02049770