Zobrazeno 1 - 10
of 40
pro vyhledávání: '"F. Ootsuka"'
Autor:
M. Kitajima, F. Ootsuka, T. Watanabe, A. Katakami, H. Nakata, K. Shirai, Yasuo Nara, Yuzuru Ohji, Masayasu Tanjyo, T. Eimori, Takayuki Aoyama
Publikováno v:
IEEE Transactions on Electron Devices. 55:1042-1049
This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivabil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::82b85b321c1d46fe4e16a9867b611d1a
https://doi.org/10.1109/ted.2008.917546
https://doi.org/10.1109/ted.2008.917546
Autor:
F. Ootsuka
Publikováno v:
IEEE Transactions on Electron Devices. 49:2345-2348
This brief presents a method to extract the equivalent oxide thickness (EOT) from the capacitance-voltage (C-V) as an asymptotic solution in strong accumulation. This method does not need the information of the flat-band voltage (V/sub FB/) or the su
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f6072355139649e710268daf553f2cc
https://doi.org/10.1109/ted.2002.805232
https://doi.org/10.1109/ted.2002.805232
Autor:
T. Matsumoto, A. Katakami, Dale C. Jacobson, Takayuki Aoyama, T. Watanabe, K. Shirai, M. Kitajima, Yuzuru Ohji, Masayasu Tanjyo, K. Saker, Noriaki Maehara, Wade A. Krull, Sei Umisedo, Yasuo Nara, T. N. Horsky, Nobuo Nagai, F. Ootsuka, Tsutomu Nagayama, Nariaki Hamamoto, T. Eimori, Yuji Koga, H. Nakata
Publikováno v:
Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08).
This paper describes the applications of cluster ion implantation for beyond 45 nm node novel devices. A) Metal/high-k MOSFET: a flash lamp annealing (FLA) has advantage of dopant diffusion-less characteristics, but it requires suitable angle control
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::107a67e0e6fe8c8d6e89985af40e5459
https://doi.org/10.1109/iwjt.2008.4540017
https://doi.org/10.1109/iwjt.2008.4540017
Publikováno v:
2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.
In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k gate dielectrics, th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::deb9f4df5583babce10d00226d1ed0df
https://doi.org/10.1109/icsict.2006.306252
https://doi.org/10.1109/icsict.2006.306252
Autor:
Tomonori Aoyama, M. Yasuhira, T. Watanabe, H. Ozaki, K. Shibata, N. Ohashi, Y. Tamura, Tsunetoshi Arikado, K. Tsujita, F. Ootsuka, Akira Mineji
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
This paper describes the 65nm-node HfSiON transistors that have been fully integrated to SRAM array. By optimizing the thermal process after the gate stack formation, the scaling of EOT has been attained without introducing additional high-k formatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f6639a3e1747c8b81cfa0e9bd718940
https://doi.org/10.1109/iedm.2004.1419334
https://doi.org/10.1109/iedm.2004.1419334
Autor:
T. Sasaki, N. Izumi, Y. Nakagawa, M. Hayashi, K. Yamashita, Tsunetoshi Arikado, K. Kiyono, H. Ozaki, H. Takada, M. Yasuhira, F. Ootsuka
Publikováno v:
IEEE International Electron Devices Meeting 2003.
This paper describes the fabrication process and the performance of 65 nm-node CMOS transistors which have ultra-shallow junctions. Flash lamp annealing enhances the drivability of pFETs with a solid phase epitaxial extension junction. The increase i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::adbfaa03bac0c555307b7249828f0870
https://doi.org/10.1109/iedm.2003.1269364
https://doi.org/10.1109/iedm.2003.1269364
Autor:
N. Inada, Yasuhiro Shimamoto, Masatada Horiuchi, Takahiro Onai, F. Ootsuka, Ryuta Tsuchiya, Jiro Yugami, K. Ohnishi, S. Tsujikawa
Publikováno v:
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
We demonstrate 40-nm CMOS transistors for the 70-nm technology node. This transistor uses a high-k offset spacer (EOS: high-epsilon offset spacer) in achieving both a short-channel and high drivability along with SiN gate dielectrics with oxygen-enri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4c68a6e1112798795a081fd1f2e6168
https://doi.org/10.1109/vlsit.2002.1015429
https://doi.org/10.1109/vlsit.2002.1015429
Publikováno v:
Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765).
In this paper, we report the improvements in the interfacial reaction between the gate dielectric and the gate electrode by adding SiN cap layer on HfO/sub 2/. We also report the drastic improvements in the gate leakage, V/sub th/ shift and NBTI.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d7cb17c8e5b6a790e429c696687e479b
https://doi.org/10.1109/iwgi.2003.159174
https://doi.org/10.1109/iwgi.2003.159174
Publikováno v:
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
A guideline of CMOS device development for high performance MPU's and ASIC's is discussed. The thermal runaway is found to limit lowest V/sub TH/. A new scaling rule including long metal wires is discussed, including effectiveness of optional wide li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4e3e9fc2057066fb7f89d6abe611667
https://doi.org/10.1109/cicc.1998.694926
https://doi.org/10.1109/cicc.1998.694926
Autor:
N. Sakuma, Kikuo Kusukawa, S. Tsujikawa, Y. Homma, F. Ootsuka, Natsuki Yokoyama, A. Miyauchi, T. Kachi, Takahiro Onai, Digh Hisamoto
Publikováno v:
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).
A compact FD-SOI CMOS fabrication process and device structure was demonstrated. A new damascene-dummy SAC process enabled to fabricate reliable contacts with ultra-thin SOI layers. We showed that using in-situ-boron-doped Si/sub x/Ge/sub 1-x/ as a g
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a50bec6af82bc1869dadd1f9cb23351c
https://doi.org/10.1109/vlsit.2000.852828
https://doi.org/10.1109/vlsit.2000.852828