Zobrazeno 1 - 10
of 47
pro vyhledávání: '"F. Feustel"'
Publikováno v:
CIRED 2021 - The 26th International Conference and Exhibition on Electricity Distribution.
Autor:
Paul F. Feustel, Huaqiu Zhang, Harold K. Kimelberg, Gary P. Schools, Wei Wang, Ting Lei, Minjie Xie, Min Zhou
Publikováno v:
Brain Research. 1247:196-211
Pretreatment of ovarectomized rats with estrogen shows long-term protection via activation of the estrogen receptor (ER). However, it remains unknown whether activation of the ER can provide protection against early neuronal damage when given acutely
Publikováno v:
Sensors and Actuators A: Physical. 99:188-193
The constitutive behaviour of Sn96.5Ag3.5, Sn95.5Ag4Cu0.5 and Sn63Pb37 solder was investigated on ultra small flip chip solder joints ( V =1×10 −12 m 3 ). In order to run experiments on these small specimens, a micro shear tester has been designed
Publikováno v:
2009 IEEE International Integrated Reliability Workshop Final Report.
In this paper we present a model to generate voltage acceleration (Vacc) values from VRDB measurements with different ramp rates. The results have been verified with TDDB measurements.
Autor:
Hans-Jürgen Engelmann, Oliver Aubel, W. Yao, C. Witt, J. Poppe, Moritz-Andreas Meyer, F. Feustel
Publikováno v:
2009 IEEE International Integrated Reliability Workshop Final Report.
In this paper we showed results on high temperature storage tests performed on 90nm, 65nm and 45nm node material with different back end of line stacks. We have seen a strong impact of BEOL stack up on resistance traces of tests at temperature of ove
Autor:
M. A. Meyer, O. Aubel, F. Feustel, H. J. Engelmann, I. Zienert, J. Poppe, D. Gehre, C. Witt, Paul S. Ho, Ehrenfried Zschech, Shinichi Ogawa
Publikováno v:
AIP Conference Proceedings.
The investigation of stress‐induced voiding (SIV) is one of the key aspects to characterize metallization reliability. Typical test methodologies include the investigation of resistance shifts during temperature storage tests at temperatures betwee
Autor:
A. Eckebracht, F. Feustel
Publikováno v:
1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).
Flip chip assembly is an attractive approach to further reduction of size and weight in electronic packaging. For cost-effective products, organic FR-4 substrates are used which require the application of underfill to ensure a sufficient long-term re
Publikováno v:
1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).
The stresses occurring in the solder joints during thermal cyclic loads have been assessed by finite element analysis and experimental tests in order to study the effect of hidden underfill imperfections on the reliability of flip chip modules. Imper
Publikováno v:
1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).
The application of flip chips is an attractive approach for many innovative products-especially portable systems. For cost reasons, the flip chip assembly has to be integrated into the existing surface mount technology. In this work, the main aspects
Publikováno v:
2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).
Delamination of underfill in flip chips is a widely accepted major cause for failure. However, there is a lack of information on the mechanism of this effect. A novel methodology is used to examine these delaminations in this paper. Instead of the ex