Zobrazeno 1 - 10
of 29
pro vyhledávání: '"F. Dulger"'
Autor:
Victoria Wang, Karthikeyan Rajagopal, S. Madhavapeddi, Siraj Akhtar, A. Jain, Charles Sestok, Hunsoo Choo, Vijayavardhan Baireddy, Scott Kaylor, Petteri Litmanen, Jaimin Mehta, Venkatesh Srinivasan, Satish V. Uppathil, A. Frank, A. Akour, Nikolaus Klemmer, Hamid Safiri, F. Dulger, Dhritiman Ghosh, S. Ramakrishnan, E. Zhang, Mounir Fares, V. Sinari, Himanshu Arora, C. Fernando
Publikováno v:
ISSCC
Increasing mobile data demands are pushing cellular network capacity. Massive MIMO base stations with large antenna arrays and smaller cell sizes demand higher integration in radio transceivers than what is available [1].
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4785a3a28f7f5421a1fd08e8ab21da0
https://doi.org/10.1109/isscc.2016.7417958
https://doi.org/10.1109/isscc.2016.7417958
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:2904-2919
We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cbaf91461bfe92cd46ff50bbbc6eb98
https://doi.org/10.1109/jssc.2011.2162769
https://doi.org/10.1109/jssc.2011.2162769
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 58:2051-2060
We propose an enhancement to the digital phase detection mechanism in an all-digital phase-locked loop (ADPLL) by randomization of the frequency reference using carefully chosen dither sequences. This dithering renders the digital phase detector, rea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b306275bdf2a8781026b4a719e26cea
https://doi.org/10.1109/tcsi.2011.2163981
https://doi.org/10.1109/tcsi.2011.2163981
Autor:
Solti Peng, Bertan Bakkaloglu, F. Dulger, Ahmed N. Mohieldin, Paul H. Fontaine, Sher Jiun Fang
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:1149-1159
A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de8c31b829fc6a4d95555879f5da502c
https://doi.org/10.1109/jssc.2006.872740
https://doi.org/10.1109/jssc.2006.872740
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:918-928
A 2.1-GHz 1.3-V 5-mW fully integrated Q-enhancement LC bandpass biquad programmable in f/sub o/, Q, and peak gain is implemented in 0.35-/spl mu/m standard CMOS technology. The filter uses a resonator built with spiral inductors and inversion-mode pM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7012a3676c0be86dd1a6cccb3dbd24d1
https://doi.org/10.1109/jssc.2003.811867
https://doi.org/10.1109/jssc.2003.811867
Publikováno v:
IEEE Transactions on Fuzzy Systems. 5:431-442
Sampled-analog circuit techniques are exploited in an application-specific integrated fuzzy controller design. A circuit library comprising a sample-and-hold amplifier, positive and negative ramp amplifiers, an inference cell, adder, and weighted add
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3539281a21f368b8f702d359cdf92d02
https://doi.org/10.1109/91.618278
https://doi.org/10.1109/91.618278
Autor:
John Wallberg, Robert Bogdan Staszewski, Chih-Ming Hung, F. Dulger, Khurram Waheed, Oren Eliezer, Sudheer Vemulapalli
Publikováno v:
ISSCC
After the first-ever all-digital PLL (ADPLL) [1] for Bluetooth radios has proven benefits of CMOS scaling and integration, demonstrators for more challenging wireless standards have emerged [2–6]. In the ADPLL, however, the digitally-controlled osc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e77f4b7c80d5ad766b9c9cc7ff22ae9f
https://doi.org/10.1109/isscc.2011.5746215
https://doi.org/10.1109/isscc.2011.5746215
Publikováno v:
CICC
This paper proposes an enhancement of the digital phase detection mechanism in an all-digital phase locked loop (ADPLL) operable at multi-GHz by randomization of the reference frequency phase by carefully chosen dither sequences. This renders the dig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::97846330e6a939920d741d72a2eddabc
https://doi.org/10.1109/cicc.2010.5617430
https://doi.org/10.1109/cicc.2010.5617430
Publikováno v:
2010 IEEE Radio Frequency Integrated Circuits Symposium.
An integrated digitally-controlled crystal oscillator (DCXO) is presented that generates both 38.4MHz and also a 32.768kHz real time clock (RTC) from a single 38.4MHz crystal. The DCXO can startup independently and transition seamlessly in and out of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d28edc66d9964e25817935a2493e2518
https://doi.org/10.1109/rfic.2010.5477325
https://doi.org/10.1109/rfic.2010.5477325
Autor:
Abdellatif Bellaouar, Sher Jiun Fang, Paul H. Fontaine, Ahmed N. Mohieldin, Michel Frechette, F. Dulger
Publikováno v:
ISCAS
A quad-band GSM/GPRS/EDGE receiver front-end including I and Q ADCs designed in 90nm digital CMOS technology is presented. The low band receiver designed for GSM850/GSM900 achieves 33dB gain, 1.9dB noise figure, 7.5dB of noise figure under blocking c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba4792c0746ebb0dd894b24fae221d5b
https://doi.org/10.1109/iscas.2006.1693270
https://doi.org/10.1109/iscas.2006.1693270