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pro vyhledávání: '"F. De Bernardinis"'
Akademický článek
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Publikováno v:
CICC
An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital converter and a dither-less digitally controlled oscillator. These
Autor:
Borivoje Nikolic, Jan M. Rabaey, Ali M. Niknejad, Alberto Sangiovanni-Vincentelli, F. De Bernardinis
Publikováno v:
Proceedings of the IEEE. 94:1070-1088
With semiconductor technology feature size scaling below 100 nm, mixed-signal design faces some important challenges, caused among others by reduced supply voltages, process variation, and declining intrinsic device gains. Addressing these challenges
Publikováno v:
ESSCIRC
A filtering ADC used to implement the complete base-band in a receiver chain is presented. Passive filtering and in-band noise shaping lead to a frequency dependent dynamic range that better fits with the system requirements of a wireless receiver. T
The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4ab3d985e862e70ea91bcbd62667ee3e
http://hdl.handle.net/11568/124529
http://hdl.handle.net/11568/124529
Publikováno v:
2006 IEEE/ACM International Conference on Computer Aided Design.
Publikováno v:
2006 Ph.D. Research in Microelectronics and Electronics.
We present an efficient solution to the digital enhancement of the characteristic of pipeline analog-to-digital converters (ADCs) given estimates for non-linearity behaviors. A third order polynomial model is assumed for non-linearity and several inv
Publikováno v:
CICC
We present the design methodology and a silicon implementation of a baseband system for use in wireless sensor network applications. Starting from the RF interface, our design process began with a system level phase inspired by the platform-based des
We address the problem of calibrating a flash analog-to-digital converter (ADC) for ultra-wide band energy-constrained receivers. To achieve a superior power efficiency the ADC exploits an unusual comparator architecture that is capable of avoiding t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::44146e128e724c17d03f92cabfd6e42b
http://hdl.handle.net/11568/104694
http://hdl.handle.net/11568/104694
Autor:
Bert Gyselinckx, G. Van der Plas, L. Van der Perre, F. De Bernardinis, Pierangelo Terreni, Pierluigi Nuzzo
Publikováno v:
DAC
We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-/spl mu/m CMOS, targeting low power ultra-wide band receivers. To minimize static power consumption, we exploit dynamic comparators with built-in digitally tunable th