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Autor:
Jose Ignacio del Agua Borniquel, Pieter Boelen, Christa Vrancken, T. Chiarella, Farid Sebaai, Philippe Absil, Evans Baiya, Rita Vos
Publikováno v:
Solid State Phenomena. :207-210
With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of th