Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Euncheol Kim"'
Publikováno v:
Journal of Low Power Electronics. 5:303-312
This paper presents an adaptive LDPC decoder design that dynamically adjusts performance to optimize gain/power for additive white Gaussian noise (AWGN) channels. The proposed decoding scheme provides constant-time decoding and thus facilitates real-
Publikováno v:
Pathology - Research and Practice. 189:1036-1043
Developing human fetal salivary glands of gestational age from 10 to 40 weeks (n = 100) and normal adult glands (n = 10) were examined for immunoreactivity to S-100 protein and its subunits S-100 alpha, S-100 beta, glial fibrillary acidic protein (GF
Publikováno v:
ICASSP (3)
This paper presents a VLSI implementation of a low-density parity check (LDPC) decoder that achieves 2.4 Gbps throughput yet permits real-time configuration of (1) rate, (2) code length, and (3) the parity equations. This decoder can be programmed in
Publikováno v:
2006 Fortieth Asilomar Conference on Signals, Systems and Computers.
The implementation complexity of the decoder for low-density parity-check codes (LDPC) is dictated by memory and interconnect requirements. We propose new LDPC decoder architectures that reduce the need of message passing memory by 80% (for standard
Autor:
Euncheol Kim, Gwan Choi
Publikováno v:
2005 Asia-Pacific Conference on Communications.
A design approach that reduces the routing complexity in a VLSI implementation of low-density parity-check (LDPC) decoder is presented. An LDPC code is a linear-block code for forward error correction, attributed by a sparse parity-check matrix. Iter
Publikováno v:
ICCD
A requirement-specific decoder design for forward error-correction in 2 Gbps optical fiber communication system is presented. Low-density parity-check codes are used to achieve high bit error rate performance. Several novel error-decoding architectur
Publikováno v:
ISCAS (2)
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to achieve a throughput of 100 Gbps. Simulation results show that this thr
Publikováno v:
2006 Fortieth Asilomar Conference on Signals, Systems & Computers; 2006, p1192-1199, 8p
Autor:
Taehee Cho, Young-Taek Lee, Euncheol Kim, Jinwook Lee, Sunmi Choi, Seungjae Lee, Dong-Hwan Kim, Wook-Kee Han, Young-Ho Lim, Jae-Duk Lee, Jung-Dal Choi, Kang-Deog Suh
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177); 2001, p28-424, 3p
Publikováno v:
2006 IEEE International Conference on Acoustics Speech & Signal Processing Proceedings; 2006, pIII-III, 1p