Zobrazeno 1 - 10
of 151
pro vyhledávání: '"Eui-Young Chung"'
Publikováno v:
IEEE Access, Vol 9, Pp 72299-72315 (2021)
For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of process, voltage, and temperature (PVT) conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating modes, each of
Externí odkaz:
https://doaj.org/article/ee06b3b76ab04eb4903f0d1a8175eb16
Autor:
Yun-Seok Oh, Eui-Young Chung
Publikováno v:
IEEE Access, Vol 9, Pp 155048-155057 (2021)
To meet the performance demands of chip multiprocessors, chip designers have increased the capacity and hierarchy of cache memories. Accordingly, a shared lower-level cache reduces conflict misses by adopting a multi-way set-associative structure wit
Externí odkaz:
https://doaj.org/article/651c5058aa7b4724be14ea67f2319fd5
Autor:
Ho Hyun Shin, Eui-Young Chung
Publikováno v:
Micromachines, Vol 10, Iss 2, p 124 (2019)
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2
Externí odkaz:
https://doaj.org/article/c2e5e4cc4fc740f7850d3acf2d0565fd
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 31:591-595
Publikováno v:
IEEE Transactions on Computers. :1-14
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:1330-1343
Publikováno v:
IEEE Embedded Systems Letters. 13:162-165
Layer-wise quantized neural networks (QNNs), which adopt different precisions for weights or activations in a layer-wise manner, have emerged as a promising approach for embedded systems. The layer-wise QNNs deploy only required number of data bits f
Autor:
Woojoo Kim, Eui-young Chung
Publikováno v:
2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).
Autor:
Eui-Young Chung, Yun-Seok Oh
Publikováno v:
IEEE Access, Vol 9, Pp 155048-155057 (2021)
To meet the performance demands of chip multiprocessors, chip designers have increased the capacity and hierarchy of cache memories. Accordingly, a shared lower-level cache reduces conflict misses by adopting a multi-way set-associative structure wit
Publikováno v:
IEEE Access, Vol 9, Pp 72299-72315 (2021)
For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of process, voltage, and temperature (PVT) conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating modes, each of