Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Ethan Schuchman"'
Autor:
Ethan Schuchman, David R. Ditzel, Ronak Singhal, Guilherme Ottoni, Gautham N. Chinya, Jamison D. Collins, Gerolf Hoflehner, Amit Kumar, Hong Wang
Publikováno v:
Conf. Computing Frontiers
While the out-of-order engine has been the mainstream micro-architecture-design paradigm to achieve high performance, Transmeta took a different approach using dynamic binary translation (BT). To enable detailed comparison of these two radically diff
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::570f193d5118e75cc64bf96a2b6e4d08
https://doi.org/10.1145/2016604.2016629
https://doi.org/10.1145/2016604.2016629
Autor:
Graham Schelle, Jamison Collins, Ethan Schuchman, Perrry Wang, Xiang Zou, Gautham Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang
Publikováno v:
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26c90b32602ce2bc474f88994e05d0f8
https://doi.org/10.1145/1723112.1723116
https://doi.org/10.1145/1723112.1723116
Autor:
Graham Schelle, Sebastian Steibl, Ralf Plate, Thorsten Mattner, Gautham N. Chinya, Franz Olbrich, Jamison D. Collins, Ronak Singhal, Perrry Wang, Hong Wang, Jim Brayton, Xiang Zou, Ethan Schuchman, Per Hammarlund
Publikováno v:
FPGA
We present an FPGA-synthesizable version of the Intel Atom processor core, synthesized to a Virtex-5 based FPGA emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transforme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0dde4960f4d5c8bdb0b07404104b7a50
https://doi.org/10.1145/1508128.1508160
https://doi.org/10.1145/1508128.1508160
Autor:
Ethan Schuchman, Hong Jiang, Tor M. Aamodt, Henry Wong, Perry Wang, Anne Bracy, Ankur Khandelwal Groen, Jamison D. Collins, Gautham N. Chinya, Hong Wang
Publikováno v:
PACT
Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cbefbccac669aa7a0a90fbf82a465f45
https://doi.org/10.1145/1454115.1454125
https://doi.org/10.1145/1454115.1454125
Autor:
Ethan Schuchman, T. N. Vijaykumar
Publikováno v:
DSN
Testing is a difficult process that becomes more difficult with scaling. With smaller and faster devices, tolerance for errors shrinks and devices may act correctly under certain condition and not under others. As such, hard errors may exist but are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b93bc8346c56fb5ff2f53e579e8fa03
https://doi.org/10.1109/dsn.2007.23
https://doi.org/10.1109/dsn.2007.23
Publikováno v:
MICRO
Power density is a growing problem in high-performance processors in which small, high-activity resources overheat. Two categories of techniques, temporal and spatial, can address power density in a processor. Temporal solutions slow computation and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70dadda4940264248ac249be09b818d1
https://doi.org/10.1109/micro.2005.14
https://doi.org/10.1109/micro.2005.14
Autor:
Ethan Schuchman, T. N. Vijaykumar
Publikováno v:
ISCA
Scaling feature size improves processor performance but increases each deviceýs susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve significantly to maintain yields. Redundancy techniques in memory have be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8a2b2e669ebd2d8dd517409f698e2515
https://doi.org/10.1109/isca.2005.44
https://doi.org/10.1109/isca.2005.44