Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Eswar Ramanathan"'
Autor:
Padraig Timoney, Joseph Luke, Mark Rovereto, Jordan Wyble, Cheng-Ting Lien, Zahir Alamgir, Eswar Ramanathan
Publikováno v:
2023 34th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Autor:
Stephanie Waite, Joshua Moore, Stephen Bradley Miner, Sara Case, Eswar Ramanathan, Wei Zhao, John Barker, Jong Soo Kim
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 30:434-439
Historically, much attention has been given to the unit processes and the integration of those unit processes to improve product yield. Less attention has been given to the wafer mini environment, either during processing or post processing. This pap
Autor:
Justin Clements, Vandana Venkatasubramanian, Christa Montgomery, Eswar Ramanathan, Jeffrey Riendeau, Veenadhar Katragadda, Alan Cusick, Edwin Soler, Qiushi Wang, Jay Mody, Lloyd Smith, Arthur Gasasira, Shafaat Ahmed, Colin Bombardier, Petrov Nicolai, Bill Evans, Raymond Krom, Martin Muthee, Michael Hatzistergos, Owen Brown, Jung Tae Hwang, Jian Qiu, Vincent Liao, Kok Hin Teo
Publikováno v:
2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Inline electrical testing in a semiconductor fabrication line is a very common method to monitor the line performance and to be able to detect any issue for the tested wafers. This helps to detect the problems much earlier. Detecting issues earlier n
Autor:
Joseph F. Shepard, Henrik Johanson, Vandana Venkatasubramanian, Jay Mody, Takmeel Qanit, Ashwini Chandrasekar, Eswar Ramanathan, Craig Child, AnbuSelvam Km Mahalingam, Lei Jiang, Brett T. Cucci, Alycia Roux, O'brien Brendan, Christa Montgomery, Bradley Morganfeld, Keith Donegan, Colin Bombardier, Sang-Kee Eah, Vijaya Rana, Ghosh Somnath, Daniel Damjanovic, Anirvan Sircar, Zhiguo Sun, Singh Sunil K, Rebekah Sheraw, Ordonio Christopher, Silvestre MaryClaire, Adam DaSilva
Publikováno v:
2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
As technology scaling continues, the selection of materials for sacrificial hard masks become very critical. Sacrificial hard masks are thin films that are used for patterning or protecting critical underlying films from damage during various process
Autor:
Eswar Ramanathan, Zhiguo Sun, Vijaya Rana, Vijayalakshmi Seshachalam, Anbu Selvam Km Mahalingam, Chauhan Kripa Nidhan, Joseph F. Shepard, Tingge Xu, Minrui Wang, Mary Claire Silvestre, Yang Bum Lee
Publikováno v:
2019 China Semiconductor Technology International Conference (CSTIC).
In advanced technology nodes, Multi-color back end of line self-aligned via (SAV) integration involves a stack of dielectric and metallic thin films to memorize the pattern transferred from different color lithography masks. We see intermittent so-ca
Autor:
Ashwini Chandrashekar, Jinping Liu, Bharat Krishnan, M. Gribelyuk, A. Zainuddin, Kassim Joseph K, T. J. Tang, Zhiguo Sun, J. Yang, Eswar Ramanathan, Shishir Ray, Ritesh Ray Chaudhuri, Tian Shen, Jay Mody, Huang Liu, Anbu Selvam Km Mahalingam, Kong Boon Yeap, Linjun Cao, Rinus T. P. Lee, Ryan Sporer, D. Damjanovic, N. Petrov
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
Nanosecond laser-induced grain growth in Cu interconnects is demonstrated for the first time using 14nm FinFET technology. We achieved a 35% reduction in Cu interconnect resistance, which delivers a 15% improvement in RC and a gain of 2 – 5% in I D
Autor:
Dhruv Singh, A. Gassaria, V. Chauhan, A. da Silva, P. Lindo, Daniel J. Dechene, M. Gribelyuk, I. Ahsan, M. Hasan, Judson R. Holt, Rod Augur, Jaeger Daniel, G. Northrop, G. Gomba, Ghosh Somnath, H. Narisetty, Basanth Jagannathan, Ting-Hsiang Hung, P. Liu, Y. Zhong, T. Gordon, Y. Fan, C. Schiller, A. Blauberg, O. Patterson, B. Morganfeld, Andres Bryant, J. Choo, T. Nigam, B. Senapati, V. Sardesai, N. Baliga, C. An, I. Ramirez, Rishikesh Krishnan, Arkadiusz Malinowski, S. Lucarini, Z. Sun, Sadanand V. Deshpande, R. Bhelkar, Mahender Kumar, Kong Boon Yeap, D. Conklin, Q. Fang, R. Gauthier, Purushothaman Srinivasan, S. Crown, M. Ozbek, Linjun Cao, G. Han, Z. Song, L. Huang, C. Serrau, R. Sweeney, M. Tan, Keith Donegan, Souvick Mitra, A. Zainuddin, P. Agnello, Balasubramanian S. Haran, Haifeng Sheng, B. Greene, A. Hassan, Tabakman Keith, Xin Wang, Sanjay Parihar, L. Cheng, M. Lagus, Jessica Dechene, D. Xu, G. Gifford, M. Zhao, Jeyaraj Antony Johnson, Y. Yan, Rick Carter, Manoj Joshi, W. Kim, Gabriela Dilliway, Jack M. Higman, S. Kalaga, Kai Zhao, Jinping Liu, A. Ogino, M. Lipinski, Amanda L. Tessier, Garo Jacques Derderian, S. Madisetti, N. Shah, Christopher Ordonio, M. Aminpur, Rakesh Ranjan, S. Saudari, Christa Montgomery, Tony Tae-Hyoung Kim, Jeric Sarad, Jae Gon Lee, Bharat Krishnan, Joseph F. Shepard, L. Hu, J. Sporre, Akil K. Sutton, Eswar Ramanathan, Cathryn Christiansen, J.H. Han, J. Lemon, Patrick Justison, Natalia Borjemscaia, Scott C. Johnson, B. Cohen, Kan Zhang, Srikanth Samavedam, G. Xu, T. Xuan, Unoh Kwon, C. Meng, Katsunori Onishi, Y. Shi, C. Huang, R. Coleman, Manfred Eller, Shreesh Narasimha, B. Kannan, J. Yang, Vivek Joshi, W. Ma, Christopher D. Sheraw, A. K. M. Mahalingam, Craig Child, E. Woodard, Tao Chu, Y. Jin, D. K. Sohn, Hasan M. Nayfeh, Mary Claire Silvestre, M. Lingalugari, G. Biery, Tian Shen, Carl J. Radens, E. Kaste, C-H. Lin, K. Han, K. Anil, Ankur Arya, Mehta Jaladhi, Jia Zeng, S.L. Liew, Michael V. Aquilino, M. Yu, M. Chen, Rohit Pal, E. Maciejewski, Stephan Grunow, Robert Fox, Rinus T. P. Lee
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over th
Autor:
Laurent Dumas, Eswar Ramanathan, Scott Hildreth, Mary Claire Silvestre, Jeffrey Riendeau, Mark Duggan
Publikováno v:
2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
As a technology ramps up to volume manufacturing, it becomes imperative that variability in yield is reduced. One of the leading contributors to this variation is coming from the wafer edge where uniformity in film thickness significantly rolls-off.
Autor:
Mary Claire Silvestre, Eswar Ramanathan, Mukesh Gogna, Christopher Ordonio, Anbu Selvam Km Mahalingam, John Schaller
Publikováno v:
2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
A conventional back end of line (BEOL) post-lithography rework process is usually considered as a non-critical process compared to other process steps in a silicon flow in advanced technologies. This paper discusses the impact of this non-critical pr
Autor:
Anbu Selvam Km Mahalingam, Qian Ge, J.-B. Laloë, San Leong Liew, Mary Claire Silvestre, Alain Laval, Balajee Rajagopalan, Robert F. Teagle, Eswar Ramanathan, Nobuyuki Takahashi, Sohana Khanal
Publikováno v:
2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
The BEOL Barrier-Seed deposition process is a key component in achieving the desired electrical and electro-migration performance while balancing the step coverage. The process also has a multifold impact on wafer yield parametric since it serves mul