Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Erwin B. Cohen"'
Autor:
Erwin B. Cohen, Jeffrey S. Zimmerman, Norman J. Rohrer, Paul D. Kartschoke, Cedric Lichtenau, Peter A. Sandon, Mathew I. Ringler, Rolf Hilgendorf, Stephen Frank Geissler, T. Pfluger, M. Canada
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:19-27
The first two members in a family of 64-bit superscalar microprocessors are presented. The 130-nm processor, which was introduced first, offers 5-way instruction dispatch, support for 4-way integer and floating-point single-instruction multiple-data
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e51cea91cae1e51a300f61442dc3863
https://doi.org/10.1109/jssc.2004.838022
https://doi.org/10.1109/jssc.2004.838022
Autor:
M. Canada, Peter A. Sandon, Paul D. Kartschoke, M. Ross, Gerard M. Salem, T. Pflueger, Cedric Lichtenau, Jay G. Heaslip, Erwin B. Cohen, J. Connor, Norman J. Rohrer, Rolf Hilgendorf, R. Floyd, Stephen Frank Geissler, Dana J. Thygesen, Mathew I. Ringler, P. McCormick
Publikováno v:
ISSCC
Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4aa2c8b51a2a0f8a719b504a0c22653
https://doi.org/10.1109/isscc.2006.1696064
https://doi.org/10.1109/isscc.2006.1696064
Publikováno v:
ISSCC
Spatially-resolved imaging of microprocessor power (SIMP) is shown to be a critical tool for measuring temperature and power distributions of a microprocessor under full operating conditions. In this paper, the SIMP technique is applied to the dual-c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b9574ecc1abf576253f01bdb3f97a77
https://doi.org/10.1109/isscc.2006.1696278
https://doi.org/10.1109/isscc.2006.1696278
Autor:
T. Pfluger, Erwin B. Cohen, M. Canada, U. Weiss, Rolf Hilgendorf, Jay G. Heaslip, Peter A. Sandon, Norman J. Rohrer, Cedric Lichtenau, Stephen Frank Geissler, Mathew I. Ringler
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
PowerTune is a power-management technique for a multi-gigahertz superscalar 64b PowerPC/sup /spl reg// processor in a 90nm technology. This paper discusses the challenges and implementation of a dynamically controlled clock frequency with noise suppr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fcf320187d44dd0e7e334d23a4ee7edd
https://doi.org/10.1109/isscc.2004.1332741
https://doi.org/10.1109/isscc.2004.1332741
Autor:
Paul D. Kartschoke, Peter A. Sandon, Dana J. Thygesen, Jay G. Heaslip, Gerard M. Salem, P. McCormick, M. Canada, Erwin B. Cohen, Jeffrey S. Zimmerman, Tobias Werner, T. Pfluger, James Allen, Norman J. Rohrer, M. Mayfield, M. Ross, Cedric Lichtenau, David Appenzeller, Mathew I. Ringler
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
A 64 b PowerPC microprocessor is introduced in 130 nm and redesigned in 90 nm SOI technology. PowerPC 970 implements a SIMD instruction set with 512 kB L2 cache. It runs at 2.0 GHz with a 1.0 GHz bus in 130 nm. The 90 nm design features PowerTune for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::826600b63af28c5b96b118d44de5b7b9
https://doi.org/10.1109/isscc.2004.1332597
https://doi.org/10.1109/isscc.2004.1332597
Autor:
Erwin B. Cohen, Jeffrey S. Zimmerman, P. McCormick, Paul D. Kartschoke, S. Charlebois, Peter A. Sandon, B. Singer, S. Geissler, Norman J. Rohrer, David Appenzeller, T. von Reyn, Gerard M. Salem
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::17620c55d20225d0fac0be28c0461bbf
https://doi.org/10.1109/isscc.2002.992979
https://doi.org/10.1109/isscc.2002.992979