Zobrazeno 1 - 10
of 61
pro vyhledávání: '"Erno Salminen"'
Publikováno v:
Microprocessors and Microsystems. 37:446-459
Today’s Multi-Processor System-on-Chips incorporate Network-on-Chips to interconnect multiple processors, memories, and accelerators. We present a freely available toolset to monitor and analyze these networks. Internal signals are pre-analyzed on
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd15a8e77332b348411726f3dc404096
https://doi.org/10.1016/j.micpro.2012.04.008
https://doi.org/10.1016/j.micpro.2012.04.008
Publikováno v:
Design Automation for Embedded Systems. 17:53-85
A Multiprocessor System-on-Chip (MPSoC) may contain hundreds of processing elements (PEs) and thousands of tasks but design productivity is lagging the evolution of HW platforms. One problem is application task mapping, which tries to find a placemen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34ff215ed17fb2d8b3923fde0d7e2bc4
https://doi.org/10.1007/s10617-013-9119-0
https://doi.org/10.1007/s10617-013-9119-0
Publikováno v:
Journal of Systems Architecture. 58:209-219
The profile for Modeling and Analysis of Real-time and Embedded systems (MARTE) is a standard UML profile promoted by the Object Management Group (OMG). MARTE defines a framework for annotating non-functional properties of embedded systems to UML mod
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c41340188c979a57722828470312542
https://doi.org/10.1016/j.sysarc.2011.01.003
https://doi.org/10.1016/j.sysarc.2011.01.003
Publikováno v:
Microprocessors and Microsystems. 32:321-329
Design space exploration is used to shorten the design time of system-on-chips (SoCs). Exploration uses abstracted system models that need to be both accurate and fast to simulate. This paper introduces a multi-level communication cost to improve the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::23b5217cfca977fb5753c89154c6f7bf
https://doi.org/10.1016/j.micpro.2008.03.011
https://doi.org/10.1016/j.micpro.2008.03.011
Publikováno v:
SiPS
Some previous theoretical studies imply that mesh and other topologies outperform bus as a System-on-Chip (SoC) interconnection. This paper shows how bus performs in a real implementation. We measure and analyze Heterogeneous IP Block Interconnection
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fd899c7b2297f44b142017c676bf31da
https://doi.org/10.1007/s11265-008-0227-1
https://doi.org/10.1007/s11265-008-0227-1
Publikováno v:
Journal of Systems Architecture. 53:795-815
Mapping of applications on a Multi-processor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formulated as finding solutions to a cost function of the algorithm perform
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44c1cf1e07e4a2439fb9672078ac9ca3
https://doi.org/10.1016/j.sysarc.2007.01.013
https://doi.org/10.1016/j.sysarc.2007.01.013
Autor:
Vesa Lahtinen, Jouni Riihimäki, Erno Salminen, Tero Kangas, Timo Hämäläinen, Kimmo Kuusilinna
Publikováno v:
Journal of Systems Architecture. 53:477-488
The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hierarchical bus, and 2-dimensional mesh on-chip networks. Performance of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f29b6ec7703ff21a7c6961800c2ab36e
https://doi.org/10.1016/j.sysarc.2006.11.006
https://doi.org/10.1016/j.sysarc.2006.11.006
Publikováno v:
IECON
Modern VLSI and FPGA chip designs utilize automated generation of the structure and component configuration for different product variations. This is based on re-usable, parametrized library components, and tools for definition, assembly, configurati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7be081ffe70c27b1d5bbd054b9d10fbe
https://doi.org/10.1109/iecon.2015.7392520
https://doi.org/10.1109/iecon.2015.7392520
Publikováno v:
2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).
In this paper we present a message-passing based interface, WarmPie, to simplify data communication and management on a Multi-Processor System-on-Chip (MPSoC). WarmPie defines a subset of Message Passing Interface (MPI) library routines. We provide C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a63520612fccae7419f124f88378085
https://doi.org/10.1109/prime.2015.7251087
https://doi.org/10.1109/prime.2015.7251087
Autor:
Tero Kangas, Kimmo Kuusilinna, Vesa Lahtinen, Erno Salminen, Jouni Riihimäki, Timo Hämäläinen
Publikováno v:
Journal of VLSI signal processing systems for signal, image and video technology. 43:185-205
This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2262060b6c88c72b65b5718d2444f7f7
https://doi.org/10.1007/s11265-006-7270-6
https://doi.org/10.1007/s11265-006-7270-6