Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Ernest Knoll"'
Publikováno v:
IEEE Micro. 41:76-84
This work presents I-DVFS: a novel approach to perform instantaneously the frequency switch during dynamic voltage frequency scaling (DVFS). The I-DVFS, unlike legacy DVFS, does not require halting an IPs execution to perform a DVFS transition, and t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08e6377d990430b8aa95228121bc5d92
https://doi.org/10.1109/mm.2021.3096655
https://doi.org/10.1109/mm.2021.3096655
Autor:
Muhammad Abozaed, Eyal Fayneh, Ernest Knoll, Michael Zelikson, Yair Talker, Marcelo Yuffe, Saher Abu Rahme, Ziv Shmuely
Publikováno v:
ISSCC
Intel's 6th generation Core processor (code named “Skylake” or SKL) was designed to enable PC performance and user-experience at smaller and thinner form factors and enable fan-less PC platforms. It required optimization to an extremely low therm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ffef104629d97be7aaa5e39e73e2390
https://doi.org/10.1109/isscc.2016.7417912
https://doi.org/10.1109/isscc.2016.7417912
Autor:
Tsvika Kurts, Michael Zelikson, Kosta Luria, Marcelo Yuffe, Moty Mehalel, Ernest Knoll, E. Altshuler, Joseph Shor, Eyal Fayneh
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:194-205
This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::476f895019ff0c08cc33b01dfec728e7
https://doi.org/10.1109/jssc.2011.2167814
https://doi.org/10.1109/jssc.2011.2167814
Publikováno v:
A-SSCC
This paper describes the Second Generation Intel® Core™ processor, a 32nm monolithic die integrating four IA cores, a processor graphics and a memory controller. The die was designed for high performance but without compromising the part power con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::86cdb1bf6b34f87121ee67cefa2f7768
https://doi.org/10.1109/asscc.2011.6123652
https://doi.org/10.1109/asscc.2011.6123652
Autor:
Eyal Fayneh, C.H. Lim, R.H. Law, Cangsang Zhao, Ernest Knoll, Feng Wang, Keng L. Wong, Rachael J. Parker
Publikováno v:
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
PLL clock generators are designed for a third-generation NetBurst/spl trade/ processor implemented in a 90nm CMOS process. A cascade configuration offers improved jitter attenuation and facilitates a wide synthesis range. Parameter design takes into
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::40e921c76d254caa3d2e9f4cd938c6ed
https://doi.org/10.1109/isscc.2003.1234366
https://doi.org/10.1109/isscc.2003.1234366