Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Ernest Antolak"'
Autor:
Ernest Antolak, Andrzej Pulka
Publikováno v:
IEEE Access, Vol 11, Pp 46979-46997 (2023)
This paper presents a simulation-based environment for verification of static task scheduling methodology in a time predictable system. Different types of processed tasks are distinguished and presented a unified system design methodology consisting
Externí odkaz:
https://doaj.org/article/48f565e96bfc491a8b71d625a3860115
Autor:
Ernest Antolak, Andrzej Pulka
Publikováno v:
IEEE Access, Vol 9, Pp 121111-121127 (2021)
The paper presents balanced heuristic techniques of static tasks scheduling in multi-core real-time system architecture. The main objective was to minimize the energy consumed by the system without causing deadlines to be missed. The authors proposed
Externí odkaz:
https://doaj.org/article/71fc0d0145bb4a04bdb916f96fa7644c
Autor:
Ernest Antolak, Andrzej Pułka
Publikováno v:
Applied Sciences, Vol 12, Iss 3, p 1630 (2022)
The paper concerns research on electronics-embedded safety systems. The authors focus on the optimization of the energy consumed by multitasking real-time systems. A new flexible and reconfigurable multi-core architecture based on pipeline processing
Externí odkaz:
https://doaj.org/article/9c2faf510026456a8a8730fc3139d748
Autor:
Andrzej Pulka, Ernest Antolak
Publikováno v:
IET Circuits, Devices & Systems. 14:648-659
The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the recon
Autor:
Andrzej PULKA, Ernest Antolak
Publikováno v:
Applied Sciences; Volume 12; Issue 3; Pages: 1630
Applied Sciences, Vol 12, Iss 1630, p 1630 (2022)
Applied Sciences, Vol 12, Iss 1630, p 1630 (2022)
The paper concerns research on electronics-embedded safety systems. The authors focus on the optimization of the energy consumed by multitasking real-time systems. A new flexible and reconfigurable multi-core architecture based on pipeline processing