A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Autor: Jeffrey C. Shearer, Philip J. Oldiges, Soon-Cheon Seo, Terry A. Spooner, Matthew E. Colburn, Ravikumar Ramachandran, V. Sardesai, Kang-ill Seo, Dinesh Gupta, Richard G. Southwick, Xiao Sun, S. Stieg, H. Cai, S. Kanakasabaphthy, Vamsi Paruchuri, R. Sampson, Lars W. Liebmann, Walter Kleemeier, Kisik Choi, Deok-Hyung Lee, Christopher Prindle, R. Divakaruni, H. Shang, Abhijeet Paul, T. Gow, D. McHerron, Dechao Guo, Fee Li Lie, J. Nam, Neeraj Tripathi, Ruilong Xie, R. Kambhampati, Muthumanickam Sankarapandian, Balasubramanian S. Pranatharthi Haran, Carol Boye, James H. Stathis, B. Hamieh, John Iacoponi, Christopher J. Waskiewicz, Geum-Jong Bae, Derrick Liu, Sanjay Mehta, Reinaldo A. Vega, Terence B. Hook, Min Gyu Sung, Jay W. Strane, D.I. Bae, Robin Chao, Hoon Kim, F. Nelson, Theodorus E. Standaert, L. Jang, Erin Mclellan, M. Celik, S. Nam, Tae-Chan Kim, C.-C. Yeh, Sean D. Burns, P. Montanini, Charan V. V. S. Surisetty, Raghavasimhan Sreenivasan, Ju-Hwan Jung, B. Lherron, S.-B. Ko, E. Alptekin, Huiming Bu, Injo Ok, Jin Cho, Mukesh Khare, J. G. Hong, Gen Tsutsui, Andreas Scholze, Bomsoo Kim, D. Chanemougame, M. Mottura, M. Weybright, H. Mallela, K. Kim, Hemanth Jagannathan, Chanro Park, J. Jenq, Donald F. Canaperi, Young-Kwan Park, R. Jung, Kangguo Cheng

Publikováno v: 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d4d82166b734af3db83f196d83853ba5
https://doi.org/10.1109/vlsit.2014.6894342

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

Autor: Scott Halle, Marcy Beard, Chiew-seng Koay, Oscar van der Straten, T. Levin, Lars Liemann, Juntao Li, D. Horak, Bryan Morris, Terry A. Spooner, S. Choi, Carol Boye, Donald F. Canaperi, Sylvie Mignot, Muthumanickam Sankarapandian, Elbert E. Huang, Chiahsun Tseng, James Hsueh-Chung Chen, Erin Mclellan, James J. Kelly, S. Fan, James J. Demarest, Nicole Saulnier, Hosadurga Shobha, Matthew E. Colburn, Balasubramanian S. Haran, Yongan Xu, Yunpeng Yin, Larry Clevenger, Christopher J. Waskiewicz, Mignot Yann, John C. Arnold

Publikováno v: 2012 IEEE International Interconnect Technology Conference.

This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) schem

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f371baddebc7d64eac10bf2c213e8ee5
https://doi.org/10.1109/iitc.2012.6251637

64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme

Autor: T. Levin, James J. Kelly, Shyng-Tsong Chen, Guillaume Landie, Stephan A. Cohen, John C. Arnold, Anthony Francis Scaduto, Takamasa Usui, Kazumichi Tsumura, M. Tagami, Hosadurga Shobha, Scott Halle, D. Horak, C-S. Koay, Sean D. Burns, Hideyuki Tomizawa, Muthumanickam Sankarapandian, Mignot Yann, M. Ishikawa, O. van der Straten, Yunpeng Yin, Donald F. Canaperi, Yongan Xu, Hirokazu Kato, Terry A. Spooner, Erin Mclellan, Matthew E. Colburn

Publikováno v: 2011 IEEE International Interconnect Technology Conference.

This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confin

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ef6cdcf3a50815fac6aedb7957a27fcf
https://doi.org/10.1109/iitc.2011.5940273

A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM

Autor: Helen Kim, Yun Tao Jiang, Susan Ng, Boris Sherman, Cornel Bozdog, Chas Archie, Alok Vaid, Ahmad D. Katnani, Mark Kelling, Narender Rana, Igor Turovets, Bin Bin Yan, Ronen Urensky, Peter Ebersbach, Matthew Sendelbach, Boaz Brill, John Allgair, Carsten Hartig, Erin Mclellan, Michael Sendler

Publikováno v: SPIE Proceedings.

Shrinking design rules and reduced process tolerances require tight control of CD linewidth, feature shape, and profile of the printed geometry. The Holistic Metrology approach consists of utilizing all available information from different sources li

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d5ddfe34680e06853a932fc865db174d
https://doi.org/10.1117/12.881632

Spacer defined double patterning for sub-72 nm pitch logic technology

Autor: Sanjay Mehta, Greg McIntyre, Martin Burkhardt, John C. Arnold, Jason P. Cain, Harry J. Levinson, Erin Mclellan, Matthew E. Colburn, Yunpeng Yin, Sivananda K. Kanakasabapathy, Ryoung-han Kim, Yuansheng Ma

Publikováno v: SPIE Proceedings.

In order to extend the optical lithography into sub-72 nm pitch regime, spacer defined double patterning as a self-aligning process option was investigated. In the sidewall defined spacer process, spacer material was deposited directly on the resist

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ba7de25829b8117a18cf0e6443e48428
https://doi.org/10.1117/12.846698