Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Eric E. Retter"'
Autor:
James A. Marcella, Jeffrey A. Stuecheli, Brad W. Michael, Stephen J. Powell, John Steven Dodson, William J. Starke, Eric E. Retter
Publikováno v:
IBM Journal of Research and Development. 62:3:1-3:13
The IBM POWER9 processor chipset provides a variety of system memory architecture interfaces to enable highly differentiated system offerings: a high bandwidth, high capacity, highly reliable, buffered architecture; a compute-density-optimized direct
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1556-1559
A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-/spl mu/m technology
Publikováno v:
ARVLSI
A new 5 V 0.8 /spl mu/m CMOS technology merges 100 K custom circuits and 4.5 Mb DRAM onto a single die that supports both high density memory and significant computing logic. One of the first chips built with this technology implements a unique Proce
Autor:
Jeffrey A. Stuecheli, Jentje Leenstra, Hung Qui Le, Dung Quoc Nguyen, Guy Lynn Guthrie, J. A. Van Norstrand, Ronald Nick Kalla, Balaram Sinharoy, Bartholomew Blaner, W. J. Starke, Eric E. Retter, Robert Alan Cargnoni, Peter Williams, Bruce Joseph Ronchetti, Charles F. Marino
Publikováno v:
IBM Journal of Research and Development. 55:1:1-1:29
The IBM POWER® processor is the dominant reduced instruction set computing microprocessor in the world today, with a rich history of implementation and innovation over the last 20 years. In this paper, we describe the key features of the POWER7® pr