Zobrazeno 1 - 10
of 95
pro vyhledávání: '"Erh-Kun Lai"'
Autor:
Zhi-Lun Liu, Alexander Grun, Wei-Chih Chien, Asit Ray, Erh-Kun Lai, I-Ting Kuo, Lynne Gignac, Christian Lavoie, Matt BrightSky, Hsiang-Lan Lung, Huai-Yu Cheng
Publikováno v:
Scientific Reports, Vol 14, Iss 1, Pp 1-9 (2024)
Abstract Ovonic threshold switching (OTS) materials that are frequently used with a resistor (1S1R) in memory devices have been found to show controllable and reversible memory properties, which could enable new memory architectures. Here, we examine
Externí odkaz:
https://doaj.org/article/f3b0531218ee42749355a1c7637dd001
Autor:
Wanki Kim, Robert L. Bruce, Wei-Chih Chien, C. W. Yeh, Hiroyuki Miyazoe, Matthew J. BrightSky, Chih-Hsiang Yang, Hsiang-Lan Lung, Fabio Carta, Asit Kumar Ray, Kuo I-Ting, Huai-Yu Cheng, Erh-Kun Lai
Publikováno v:
IEEE Transactions on Electron Devices. 65:5172-5179
High endurance ovonic threshold switch (OTS, here, TeAsGeSiSe-based) is integrated with phase change memory (PCM, here, doped Ge2Sb2Te5) to form a 3-D stackable pillar-type device. With the help of an etch buffer layer and a damage-free pillar reacti
Autor:
H. Y. Ho, Asit Kumar Ray, Erh-Kun Lai, Kuo I-Ting, L. Buzi, Huai-Yu Cheng, Marinus Hopstaken, Wanki Kim, H.L. Lung, Fabio Carta, Y. C. Chou, C. W. Yeh, Christian Lavoie, Robert L. Bruce, Lynne Gignac, C. H. Yang, Wei-Chih Chien, Nanbo Gong, Cheng-Wei Cheng, Matthew J. BrightSky, Ming-Hsiu Lee
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
By incorporating Si into AsSeGe system, we demonstrate a 3D stackable OTS+PCM memory in a 1k by 1k cross-point memory array with extremely low $\mathrm{V}_{\mathrm{tS}}$ drift (~0V after 3 days from programming), wide $\mathrm{V}_{\mathrm{tS}}/\mathr
Autor:
C. W. Yeh, Erh-Kun Lai, Y. C. Chou, Wanki Kim, Robert L. Bruce, H.L. Lung, Yu-Yu Lin, Ning Li, Matthew J. BrightSky, C. H. Yang, Fabio Carta, Henry K. Utomo, Cheng-Wei Cheng, H. Y. Ho, Christopher P. Miller, Huai-Yu Cheng, L. Buzi, Asit Kumar Ray, Nanbo Gong, T. Perri, Lynne Gignac, Kuo I-Ting, Wei-Chih Chien
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
We present the first MLC operation for OTS-PCM with comprehensive operation algorithm study. An ADM chip with fast write speed ( 10 9 cycles) are shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell operation up to
Autor:
Kuang-Hao Chiang, Yu-Yu Lin, Jau-Yi Wu, Tseung-Yuen Tseng, Ming-Hsiu Lee, Chih-Yuan Lu, Erh-Kun Lai, Yu-Hsuan Lin, Dai-Ying Lee, Feng-Ming Lee
Publikováno v:
IEEE Electron Device Letters. 37:1426-1429
Resistance of transition metal oxide (TMO) resistive random access memory (ReRAM) depends sharply on temperature, resulting in drastic memory window loss at high temperature. Thus, it is difficult to design the ReRAM that can serve a wide range of op
Autor:
Y. F. Lin, M. Briahtxky, Y. C. Chou, Erh-Kun Lai, Huai-Yu Cheng, H.L. Lung, Cheng-Wei Cheng, C. H. Yang, Kuo I-Ting, A. Rav, Wei-Chih Chien, Nanbo Gong, Robert L. Bruce, Fabio Carta, C. W. Yeh, Lynne Gignac, H. Y. Ho, John M. Papalia, Wanki Kim
Publikováno v:
2019 Symposium on VLSI Technology.
We present a scaling study toward lZnm node 3D Cross-point PCM (XPCM) for Storage Class Memory (SCM) applications. The low operation current, and low metal line loading resistance are desired to avoid a wide operation voltage distribution in a cross-
Superb Endurance and Appropriate Vth of PCM Pillar Cell using Buffer Layer for 3D Cross-Point Memory
Autor:
Matthew J. BrightSky, Huai-Yu Cheng, N. Gang, Cheng-Wei Cheng, Erh-Kun Lai, C. W. Yeh, Asit Kumar Ray, Robert L. Bruce, H.L. Lung, Kuo I-Ting, L.M. Gignac, Fabio Carta, C. H. Yang, Wanki Kim, John M. Papalia, Wei-Chih Chien
Publikováno v:
2019 IEEE 11th International Memory Workshop (IMW).
A reliability study for phase change memory (PCM) pillar cell is performed. We found that without a buffer layer, the PCM pillar cell shows earlier endurance failure than its mushroom counterpart, and the underlying failure mechanism is attributed to
Autor:
Erh-Kun Lai, Robert L. Bruce, Huai-Yu Cheng, Fabio Carta, H.L. Lung, Wanki Kim, Lynne Gignac, Cheng-Wei Cheng, C. W. Yeh, Matthew J. BrightSky, Hiroyuki Miyazoe, Nanbo Gong, Asit Kumar Ray, Kuo I-Ting, Wei-Chih Chien, C. H. Yang, John M. Papalia
Publikováno v:
2019 IEEE 11th International Memory Workshop (IMW).
A reliability study for PCM and OTS intermixing was addressed. The buffer layer between PCM and OTS plays a key role in preventing PCM/OTS intermixing after BEOL processing thermal treatment. Besides cycling endurance, performance degradation due to
Autor:
Wei-Chih Chien, Lynne Gignac, Erh-Kun Lai, Cheng-Wei Cheng, F. M. Lee, Wanki Kim, H. Y. Ho, Huai-Yu Cheng, C. H. Yang, H.L. Lung, Robert L. Bruce, Christian Lavoie, Fabio Carta, Ming-Hsiu Lee, C. W. Yeh, Y. F. Lin, Matthew J. BrightSky, Asit Kumar Ray, Kuo I-Ting
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
New selector materials with very-low I OFF and optimum V th . based on As-Se-Ge chalcogenides are studied. An optimized composition is proposed, which achieves a good trade-off between thermal stability and cycling endurance and it is successfully in
Autor:
Fabio Carta, Asit Kumar Ray, Kuo I-Ting, Matthew J. BrightSky, C. W. Yeh, Robert L. Bruce, Wei-Chih Chien, C. H. Yang, Erh-Kun Lai, H.L. Lung, Wanki Kim, Hiroyuki Miyazoe, Huai-Yu Cheng
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
For the first time published, high endurance OTS (ovonic threshold switch, here, TeAsGeSiSe-based) is integrated with PCM (here, doped Ge2Sb2Te5) to form a 3D stackable pillar type device. With the help of an etch buffer layer and a damage-free pilla