Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Emeric De Foucauld"'
Autor:
Zhaopeng Wei, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Jerome Prouvee, Benjamin Blampey
Publikováno v:
Active and Passive Electronic Components, Vol 2019 (2019)
Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology
Externí odkaz:
https://doaj.org/article/73bcb8515dc1463dbd1ad7f806d71cfd
Publikováno v:
Solid-State Electronics. 200:108538
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::192de86936d8d13d5467ecd6c506805a
https://doi.org/10.1016/j.sse.2022.108538
https://doi.org/10.1016/j.sse.2022.108538
Autor:
Philippe Lorenzini, Gilles Jacquemod, Frederic Hameau, Emeric de Foucauld, Zhaopeng Wei, Yves Leduc
Publikováno v:
Journal of Low Power Electronics. 12:64-73
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa46016cfa41fe7765b04e0301ce274a
https://doi.org/10.1166/jolpe.2016.1421
https://doi.org/10.1166/jolpe.2016.1421
Publikováno v:
Frontiers of Materials Science. 9:156-162
MOS bulk transistor is reaching its limits: sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage (VT) and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::244ddc5ce672f0101640591627db9131
https://doi.org/10.1007/s11706-015-0288-6
https://doi.org/10.1007/s11706-015-0288-6
Publikováno v:
NEWCAS
In this paper, we propose a new complementary topology which could reduce the variability of the cells and offer new topologies with better performances. Using the unique advantage of FDSOI technology “back-gate control”, the complementary struct
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7994b941369851705db27c9e11c9b89
https://doi.org/10.1109/newcas.2017.8010120
https://doi.org/10.1109/newcas.2017.8010120
Publikováno v:
ICECS
An analog clock generator built with complementary logic cells in UTBB-FDSOI delivers the robust symmetrical clocks required to control high-performance differential switched-capacitor circuits. Using back-gate feedback and sizing respecting static a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c77fc6e67befb6169b04d513986447b8
https://doi.org/10.1109/icecs.2016.7841266
https://doi.org/10.1109/icecs.2016.7841266
Autor:
Alexandre Siligaris, Salvador Mir, Haralampos-G. Stratigopoulos, Athanasios Dimakos, Emeric De Foucauld
Publikováno v:
Design, Automation & Test in Europe Conference
Design, Automation & Test in Europe Conference, Mar 2016, Dresden, Germany
DATE
Design, Automation & Test in Europe Conference, Mar 2016, Dresden, Germany
DATE
This paper addresses the high-volume production test problem for millimeter-wave (mm-Wave) circuits. Bit error rate testing is the only feasible solution nowadays for mm-Wave transceivers, but is extremely costly and challenging to be implemented in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f54ad0c0c8b7e19aafe1c5a47002264d
https://hal.sorbonne-universite.fr/hal-01359620
https://hal.sorbonne-universite.fr/hal-01359620
Autor:
Bernard Viala, Jean-Philippe Michel, Mouna El Bakkali, Francis Chan Wai Po, Emeric de Foucauld
Publikováno v:
Microelectronics Journal. 42:233-238
We present in this paper a new technique of matching impedances. It consists in replacing a fixed inductor in a matching network by a variable one, and its value is able to change with the load impedance. In the study, the fixed inductance considered
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f0a8acc1362dad6b05ee8cc96212ec2
https://doi.org/10.1016/j.mejo.2010.08.004
https://doi.org/10.1016/j.mejo.2010.08.004
Publikováno v:
Analog Integrated Circuits and Signal Processing. 53:43-51
In this paper, the design of two VCOs for wireless multi-standard applications is presented. The oscillation frequencies are 5.2 and 3.3 GHz. These circuits have been produced using CMOS/SOI technology, with body voltage to control power consumption
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc16b1914b48851eca4dafec39a9ed73
https://doi.org/10.1007/s10470-007-9077-1
https://doi.org/10.1007/s10470-007-9077-1
Autor:
Jad Modad, Frederic Hameau, Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Philippe Lorenzini, Gilles Jacquemod
Publikováno v:
2015 International Workshop on CMOS Variability (VARI).
This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9dbc566a3356fe01b471f2907c188b67
https://doi.org/10.1109/vari.2015.7456557
https://doi.org/10.1109/vari.2015.7456557