Zobrazeno 1 - 10
of 62
pro vyhledávání: '"Elio, Consoli"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1921-1932
A novel reconfigurable switched-capacitor “EChO” Power Management Unit is introduced for ultra-low power duty-cycled integrated systems (e.g., sensor nodes for critical event monitoring). “EChO” reduces the energy cost associated with sleep-t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::66e6919b6d87f3b926c3fe5c69883e23
https://doi.org/10.1109/jssc.2013.2258816
https://doi.org/10.1109/jssc.2013.2258816
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:284-295
In this paper we show that, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay minimization is worthwhile to improve the performance in high-speed designs. In part
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::33c942eaaf3a97b5f8ce9d57691333b1
https://doi.org/10.1109/tvlsi.2010.2098426
https://doi.org/10.1109/tvlsi.2010.2098426
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 59:159-169
In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::75ec6b5980d1a83a2d848fb8158cfa5b
https://doi.org/10.1109/tcsi.2011.2158704
https://doi.org/10.1109/tcsi.2011.2158704
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19:725-736
In this paper (split into Parts I and II), an extensive comparison of existing flip-flop (FF) classes and topologies is carried out. In contrast to previous works, analysis explicitly accounts for effects that arise in nanometer technologies and affe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2286935c7b6e8a0ff9fdf0148b8ccef0
https://doi.org/10.1109/tvlsi.2010.2041376
https://doi.org/10.1109/tvlsi.2010.2041376
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19:737-750
In Part II of this paper, a comparison of the most representative flip-flop (FF) classes and topologies in a 65-nm CMOS technology is carried out. The comparison, which is performed on the energy-delay-area domain, exploits the strategies and methodo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ec72a5aca480fc7970682af15ceaa94b
https://doi.org/10.1109/tvlsi.2010.2041377
https://doi.org/10.1109/tvlsi.2010.2041377
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 57:1583-1596
In this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e46c8d628d708f1f5bb6d5c3787b8f3a
https://doi.org/10.1109/tcsi.2009.2033538
https://doi.org/10.1109/tcsi.2009.2033538
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 57:1273-1286
In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::50e55cfacd6635a5b691d269a33aea89
https://doi.org/10.1109/tcsi.2009.2030113
https://doi.org/10.1109/tcsi.2009.2030113
This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the ta
Publikováno v:
Flip-Flop Design in Nanometer CMOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddc77cea28cc5766a3d7f50486327a5b
https://doi.org/10.1007/978-3-319-01997-0
https://doi.org/10.1007/978-3-319-01997-0
In this paper, the impact of variations on single-edge triggered flip-flops (FFs) is evaluated for a wide range of topologies. In particular, this Part II explicitly considers sources of variations such as voltage, temperature and variations induced
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::551d052189665bcea191a7571561b5c8
http://hdl.handle.net/20.500.11769/39875
http://hdl.handle.net/20.500.11769/39875