Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology

Autor: Jerome Juillard, Chuan Shan, Elena Blokhina, Anton Korniienko, Eric Colinet, M. Javidan, Eldar Zianbetov, Olivier Billoint, Francois Anceau, Dimitri Galayko

Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66 (10), pp.1673-1677. ⟨10.1109/TCSII.2019.2932029⟩
IEEE Transactions on Circuits and Systems II: Express Briefs, Institute of Electrical and Electronics Engineers, 2019, 66 (10), pp.1673-1677. ⟨10.1109/TCSII.2019.2932029⟩

This brief presents an active distributed clock generator for manycore systems-on-chip consisting of a $10\times 10$ network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequ

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2602071fab925a1aa2e01aeebedcb60c
https://hal.science/hal-02318785

Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing

Autor: Edith Beigne, G. Di Pendina, J. F. Christmann, Eldar Zianbetov

Publikováno v: ECCTD
2015 European Conference on Circuit Theory and Design (ECCTD)
2015 European Conference on Circuit Theory and Design (ECCTD), Aug 2015, Trondheim, Norway
HAL

Autonomous wireless sensor nodes are creating a great opportunity for non-volatile memories as, very often, those systems are recovering their energy from their surrounding environment. Those systems require low leakage and data backup when the circu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5c056bc84ae4123020d0a7521b0ea16c
https://doi.org/10.1109/ecctd.2015.7300042

A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs

Autor: Olivier Billoint, Dimitri Galayko, Eldar Zianbetov, Chuan Shan, Franccois Anceau

Publikováno v: New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International
New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International, IEEE-CASS, Jun 2015, Grenoble, France. ⟨10.1109/NEWCAS.2015.7182059⟩
NEWCAS

International audience; This paper presents a Cartesian network of CMOS oscillators distributed on a chip and synchronized by a network of all-digital PLLs in phase and in frequency. Such a network may be used for generation of a global clock in larg

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fb978180b6a2a62b9952e5640ef628ba
https://hal.archives-ouvertes.fr/hal-01521883

Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

Autor: Edith Beigne, Eldar Zianbetov, G. Di Pendina

Publikováno v: Journal of Applied Physics
Journal of Applied Physics, American Institute of Physics, 2015, 117 (17), pp.17B517
HAL
Journal of Applied Physics, 2015, 117 (17), pp.17B517

Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3160eed832f136998027086303b3a9eb
https://hal.archives-ouvertes.fr/hal-01976650

'Swimming pool'-like distributed architecture for clock generation in large many-core SoC

Autor: Francois Anceau, Dimitri Galayko, Eldar Zianbetov, Chuan Shan

Publikováno v: ISCAS

—Synchronization is an issue of significant impor-tance in large-scale, distributed and high-speed systems. Tradi-tional globally synchronous approach is no longer viable due to severe wire delay. Solutions such as "Globally Asynchronous, Lo-cally

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::17980fdbd9fb93dc0fab4d3156772da2
https://doi.org/10.1109/iscas.2014.6865747