Zobrazeno 1 - 5
of 5
pro vyhledávání: '"El Mehdi ABDALI"'
Publikováno v:
2021 4th International Symposium on Advanced Electrical and Communication Technologies (ISAECT).
Publikováno v:
RSP
31st International Workshop on Rapid System Prototyping (RSP)
31st International Workshop on Rapid System Prototyping (RSP), Sep 2020, Virtual Conference (ESWEEK), France
31st International Workshop on Rapid System Prototyping (RSP)
31st International Workshop on Rapid System Prototyping (RSP), Sep 2020, Virtual Conference (ESWEEK), France
International audience; Hardware in the loop simulation has become a fundamental tool for the safe and rapid development of embedded systems. Dynamically and partially reconfigurable FPGA provide an energy efficient solution for high performance comp
Autor:
El Mehdi Abdali, Abderrahmane Walid Hanniche, Maxime Pelcat, François Berry, Jean-Philippe Diguet
Publikováno v:
ICDSC
Robust object tracking is a crucial enabler of many computer vision applications. An embedded object tracker must, in addition to respecting real-time requirements, robustly update the position of the tracked object in the captured images and be able
Publikováno v:
ReCoSoC
2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017)
12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017)
12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017), Jul 2017, Madrid, Spain. ⟨10.1109/ReCoSoC.2017.8016160⟩
2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017)
12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017)
12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017), Jul 2017, Madrid, Spain. ⟨10.1109/ReCoSoC.2017.8016160⟩
International audience; An ever larger share of FPGAs are supporting Dynamic and Partial Reconfiguration (DPR). A reconfigurable point-to-point interconnect (ρ-P2P) is a communication mechanism based on DPR that swaps between different precomputed c
Publikováno v:
ICDSC
International audience; Field-programmable gate array (FPGAs) are classified as high efficient computational execution platform. However their limited density makes them not suitable for highly demanding algorithms. The Partial Dynamic Reconfiguratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b05ee7d14d9c5a2aa353518a522ac784
https://hal-univ-rennes1.archives-ouvertes.fr/hal-01380635
https://hal-univ-rennes1.archives-ouvertes.fr/hal-01380635