Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Ejaz Haq"'
Autor:
Syed Ali, Dong-Gi Lee, Ejaz Haq, Jong-Chang Son, Heung-Kwun Oh, Tae-Sung Jung, Seung-Keun Lee, Kang-Deog Suh, Jin-Sun Yum, Do-Chan Choi, Myong-Jae Kim, Myung-Sik Yong, Sung-Hee Cho, Woung-Moo Lee, Hyung-Kyu Lim, Byung-Soon Choi, Sung-Bu Jun, San-Hong Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:1748-1757
A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random acces
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::38e8effbeedbeaaa2fb22b6fa024f935
https://doi.org/10.1109/4.641697
https://doi.org/10.1109/4.641697
Autor:
Keum-Yong Kim, Ejaz Haq, Kye-Hyun Kyung, Kinam Kim, Bok-Moon Kang, Moon-Hae Son, Chang-Hyun Kim, Hyung-Kyu Lim, Soo-In Cho, K. H. Lee, Jai-Hoon Sim, Sang-Bo Lee, Jae-Gwan Park, Jong-Woo Park, Jung-Hwa Lee, Seung-Moon Yoo, Jei-Hwan Yoo, Joungho Kim, Jinman Han, Byung-sik Moon, Kang-yoon Lee, Kyu-Chan Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1635-1644
This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe8f35bf377499dd5f1a434eea274fb8
https://doi.org/10.1109/jssc.1996.542308
https://doi.org/10.1109/jssc.1996.542308
Autor:
Yun-Ho Choi, Cheol-soo Kim, Ejaz Haq, Dae-Je Chin, Soo-In Cho, Churoo Park, J. Karp, Seung-Hoon Lee, Si-Yeol Lee, Myung-Ho Kim, Hyun-Soon Jang, Ho-Cheol Lee, Tae-Jin Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:529-533
In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 1
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d807baec398de79803c159e91011088b
https://doi.org/10.1109/4.280704
https://doi.org/10.1109/4.280704
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:499-503
Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two Ni
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::abc33c997fe8ea4095ce53ac452bf0b3
https://doi.org/10.1109/4.210034
https://doi.org/10.1109/4.210034
Autor:
Chan Jong Park, Jung-Hwa Lee, Sei Seung Yoon, Hyung-Dong Kim, Dong Il Seo, Ejaz Haq, Byung-Chul Kim, Seung-Moon Yoo, Jeong Se-Jin, Chang Gyu Hwang, Tae-Seong Jang, Jin Man Han, Chang Sik Choi, Soo-In Cho
Publikováno v:
Proceedings of 1994 IEEE Symposium on VLSI Circuits.
A 256M DRAM featuring register controlled low power self refresh without toggling of internal addresses or predecoders, activation of all row lines in quick succession for rapid burn-in at wafer level and hierarchical I/O line scheme with flexible re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba86bc2d54e13242f05a53bff80c064b
https://doi.org/10.1109/vlsic.1994.586228
https://doi.org/10.1109/vlsic.1994.586228
Autor:
Jae-Hyeong Lee, Do-Chan Choi, Soo-In Cho, Gi-Won Cha, Jong-Woo Park, Kyu-Pil Lee, Keum-Yong Kim, Dong-Soo Jun, Young-Rae Kim, Ejaz Haq, Sang-Bo Lee, Hyung-Kyu Lim
Publikováno v:
Proceedings of 1994 IEEE Symposium on VLSI Circuits.
with wide operating voltage range of 1.8~ to 3.6~ for battery based portable applications. Low power during data retention is obtained with Vcc and temperature variable self refresh which is programmable after packaging using electrical fuses. High p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc0b878f8b25eb248487abf0f0b84e5d
https://doi.org/10.1109/vlsic.1994.586227
https://doi.org/10.1109/vlsic.1994.586227
Publikováno v:
1992 Symposium on VLSI Circuits Digest of Technical Papers.
The authors describe a variable V/sub cc/ design technique to extend battery life. Several special circuits for low V/sub cc/, compensated DC generators and wordline drivers are proposed. These are implemented in a 16 M DRAM using 1 polycide, 3 poly,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05f4d3fd328dcdab5a43c7098f814e8b
https://doi.org/10.1109/vlsic.1992.229267
https://doi.org/10.1109/vlsic.1992.229267
Autor:
Jong-Woo Park, Chang-Hyun Kim, Jinman Han, Kang-yoon Lee, Jei-Hwan Yoo, Byung-sik Moon, Moon-Hae Son, Joungho Kim, Jae Gwan Park, Ejaz Haq, Keum-Yong Kim, Seung-Moon Yoo, Soo-In Cho, K. H. Lee, Jai-Hoon Sim, Hyung-Kyu Lim, Kinam Kim, Bok-Moon Kang, Jung Hwa Lee, Sang-Bo Lee, Kye-Hyun Kyung, Kyu Chan Lee
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
This 32-bank 1 Gb DRAM features: (1) a merged bank architecture (MBA) that results in only 3% die area penalty for 32-bank operation; (2) a source-synchronous I/O interface (SSI) that achieves 1 GB/s bandwidth with low power consumption; (3) flexible
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f593412634f85f7b9aef089242aa32d
https://doi.org/10.1109/isscc.1996.488725
https://doi.org/10.1109/isscc.1996.488725
Autor:
null Tae-Sung Jung, null Do-Chan Choi, null Sung-Hee Cho, null Myong-Jae Kim, null Seung-Keun Lee, null Byung-Soon Choi, null Jin-Sun Yum, null San-Hong Kim, null Dong-Gi Lee, null Jong-Chang Son, null Myung-Sik Yong, null Heung-Kwun Oh, null Sung-Bu Jun, null Woung-Moo Lee, null Ejaz Haq, null Kang-Deog Suh, null Syed Ali, null Hyung-Kyu Lim
Publikováno v:
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
A 3.3V 16Mb nonvolatile memory has read and write operations fully DRAM-compatible except a longer RAS precharge time after write. Most systems with high-performance processors use a shadow nonvolatile memory uploaded to a fast DRAM to obtain zero wa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4551e6d01aabea896d7922dbf648d5bf
https://doi.org/10.1109/isscc.1997.585457
https://doi.org/10.1109/isscc.1997.585457
Publikováno v:
Symposium on VLSI Circuits.
Achieving fast access time at low voltage and low power is still a demanding task for high density SRAM. Although some previous BiCMOS designs operate at 3.3 V, the access time is usually slower than at 5 V. The speed is mainly dependent on the I/O i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::47b2c5458bbbb7993d8321a1ca03b14e
https://doi.org/10.1109/vlsic.1993.920563
https://doi.org/10.1109/vlsic.1993.920563