Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Eishi Arima"'
Publikováno v:
Workshop Proceedings of the 51st International Conference on Parallel Processing.
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783031232190
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::be706a7adccb87bd9842c11ae5fc47dd
https://doi.org/10.1007/978-3-031-23220-6_14
https://doi.org/10.1007/978-3-031-23220-6_14
Publikováno v:
Architecture of Computing Systems ISBN: 9783031218668
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ce8040466be7841b09c98b684f7cad0
https://doi.org/10.1007/978-3-031-21867-5_4
https://doi.org/10.1007/978-3-031-21867-5_4
Publikováno v:
COOL CHIPS
Future HPC systems, including post-exascale supercomputers, will face severe problems such as the slowing-down of Moore's law and the limitation of power supply. To achieve desired system performance improvement while counteracting these issues, the
Publikováno v:
CLUSTER
The supercomputer “Fugaku”, which recently ranked number one on multiple supercomputing lists, including the Top500 in June 2020, has various power control features, such as (1) an eco mode that utilizes only one of two floating-point pipelines w
Autor:
Eishi Arima
Publikováno v:
DSD
In modern microprocessors, lower level cache memories are usually implemented as unified caches where different classes of cachelines such as data, instructions, and Page Table Entries (PTEs) coexist. Particularly, frequent PTE accesses following aft
Autor:
Martin Schulz, Eishi Arima
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783030507428
ISC
ISC
The ever increasing demand for higher memory performance and—at the same time—larger memory capacity is leading the industry towards hybrid main memory designs, i.e., memory systems that consist of multiple different memory technologies. This tre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::46572a39e8f043b2665a41686cf0ad18
https://doi.org/10.1007/978-3-030-50743-5_24
https://doi.org/10.1007/978-3-030-50743-5_24
Autor:
Takashi Nakada, Atsushi Kawasumi, Shinobu Fujita, Hiroyuki Hara, Keiko Abe, Junichi Ito, Naoharu Shimomura, Satoshi Takaya, Eishi Arima, Kazutaka Ikegami, Keiichi Kushida, Hiroki Noguchi, Hiroshi Nakamura
Publikováno v:
ISSCC
Two performance gaps in the memory hierarchy, between CPU cache and main memory, and main memory and mass storage, will become increasingly severe bottlenecks for computing-system performance. Although it is necessary to increase memory capacity to f
Autor:
Eishi Arima, Takashi Nakada, Shinobu Miwa, Shinobu Fujita, Susumu Takeda, Kumiko Nomura, Hiroki Noguchi, Hiroshi Nakamura
Publikováno v:
2015 International SoC Design Conference (ISOCC).
This paper describes state-of-the-art STT-MRAM, which can drastically save energy consumption dissipated in cache memory system compared with conventional SRAM-based ones. This paper also presents how to build cache memory hierarchy with both the sta
Autor:
Hiroki Noguchi, Hiroshi Nakamura, Shinobu Miwa, Takashi Nakada, Shinobu Fujita, Eishi Arima, Susumu Takeda
Publikováno v:
ICCD
Implementing last level caches (LLCs) with STT-MRAM is a promising approach for designing energy efficient microprocessors due to high density and low leakage power of its memory cells. However, peripheral circuits of an STT-MRAM cache still suffer f