Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Effiong Ibok"'
Publikováno v:
IEEE Transactions on Electron Devices. 47:1349-1354
In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n/sup +/ poly-SiO/sub 2/-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and cur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f79a2eccefa2c44027d8e9495378bd4
https://doi.org/10.1109/16.848276
https://doi.org/10.1109/16.848276
Publikováno v:
IEEE Transactions on Electron Devices. 46:1650-1655
This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-/spl Aring/ o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49983ed7853b44e57b0726fe14a89ec9
https://doi.org/10.1109/16.777153
https://doi.org/10.1109/16.777153
Autor:
Shyam G. Garg, Effiong Ibok
Publikováno v:
Journal of The Electrochemical Society. 140:2927-2937
Low pressure chemically vapor deposited polysilicon deposition was studied from 525 to 650 C. The silicon appears to be amorphous with a smooth surface up to 550 C and completely crystalline above 600 C. The transition region is found to be from 560
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90b53aeb0fd3cbb6102a6badc72b4711
https://doi.org/10.1149/1.2220934
https://doi.org/10.1149/1.2220934
Publikováno v:
IEEE Electron Device Letters. 20:442-444
Ultrathin oxynitride using plasma assisted deposition was evaluated against thermal oxide and nitrided thermal oxide as an alternative direct tunneling gate dielectric to thermal oxide in the 2.5-nm regime. The oxynitride showed an enhanced high fiel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62220c82edb3b0bc1a154a82f0b42d80
https://doi.org/10.1109/55.784446
https://doi.org/10.1109/55.784446
Autor:
Shyam G. Garg, Sanjay K. Banerjee, Chengqing Hu, David L. Kencke, Effiong Ibok, Basab Bandyopadhyay, Bradley T. Moore, Robert B. Richart
Publikováno v:
IEEE Electron Device Letters. 16:500-502
A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROM's. By lowering the drain voltage and increasing the magnitude o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b909e01e0234e069933ce9d444a6ec5
https://doi.org/10.1109/55.468280
https://doi.org/10.1109/55.468280
Autor:
Sanjay K. Banerjee, Chengqing Hu, Shyam G. Garg, Basab Bandyopadhyay, Effiong Ibok, David L. Kencke
Publikováno v:
Applied Physics Letters. 66:1638-1640
Metal‐oxide‐semiconductor (MOS) capacitance–voltage (C–V) characteristics in the accumulation mode have been measured and simulated for polycrystalline Si gate MOS capacitors with various oxide thicknesses (40–200 A) on p‐type (100) Si su
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8e3f9ea2e5ca31faac942280d8c6fd9
https://doi.org/10.1063/1.113877
https://doi.org/10.1063/1.113877
Autor:
Khaled Ahmed, Ming-Ren Lin, David Bang, Geoffrey Choh-Fei Yeap, Miryeong Song, Qi Xiang, Effiong Ibok
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
Summary form only given. In this paper, we report the performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling (DT) gate oxides. Both pure oxides and nitrided oxides down to 17 /spl Aring/ were investigated. For a L/sub g/ o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d72ea41c3e1daea76d207a5f3c42ee36
https://doi.org/10.1109/vlsit.1998.689240
https://doi.org/10.1109/vlsit.1998.689240
Autor:
Geoffrey Choh-Fei Yeap, Effiong Ibok, Miryeong Song, Khaled Ahmed, Ming-Ren Lin, Qi Xiang, David Bang
Publikováno v:
56th Annual Device Research Conference Digest (Cat. No.98TH8373).
Performance and reliability of sub-100 nm gate length devices using a dual gate and shallow trench isolated CMOS technology were investigated. Ultra-thin direct tunneling (DT) thermal, nitrous and nitric oxides as thin as 1.3 nm are used. Only N-MOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::baa4bb0b556d79d31dd8f63d69019ba7
https://doi.org/10.1109/drc.1998.731099
https://doi.org/10.1109/drc.1998.731099
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
Continued scaling of mainstream planar CMOS transistor technology into the deep-sub-100 nm regime is increasingly challenging but possible. In this paper, we report bulk-silicon planar CMOS transistors with the physical gate length scaled down to 15
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::873d97d7bde5f37de25e88a59d97e38a
https://doi.org/10.1109/iedm.2001.979669
https://doi.org/10.1109/iedm.2001.979669
Publikováno v:
SPIE Proceedings.
This paper describes a methodology that has been incorporated into a fully integrated measurement system, the n&k Analyzer, that determines simultaneously the thickness, energy band gap, andn and k spectra (from 190 to 900 nm) of various forms of sil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8cadeb651d07964a138892054451bcf2
https://doi.org/10.1117/12.250929
https://doi.org/10.1117/12.250929