Výsledky vyhledávání - "Effective resolution bandwidth"

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An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS

Autor: Kyoung-Jun Moon, Eun-Ji An, Dong-Ryeol Oh, Won-Mook Lim, Ye-Dam Kim, Seung-Tak Ryu

Publikováno v: IEEE Journal of Solid-State Circuits. 56:1216-1226

An 8-bit 1-GS/s asynchronous loop-unrolled (LU) successive approximation register (SAR)-Flash hybrid analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs) is presented. The proposed ADC is a combination of an asynchronous LU-

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::85f49fd39d82725baf1f9f108f07e746
https://doi.org/10.1109/jssc.2020.3044624

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Akademický článek

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A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction

Autor: Xiao Wang, Hanjun Jiang, Chengwei Wang, Zhihua Wang, Peilin Yang, Fule Li

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:2004-2013

This article presents a 14-bit 200-Ms/s pipelined analog-to-digital converter (ADC) for wide input frequency range. The ADC adopts a sample-and-hold amplifier-less (SHA-less) 3.5-bit front-end stage. A dedicated path combining architecture is propose

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0a1d1781654610f1a569e624ebcd31b5
https://doi.org/10.1109/tvlsi.2020.3006147

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A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration

Autor: Jiaji Mao, Hegong Wei, Sai-Weng Sin, Mingqiang Guo, Rui P. Martins

Publikováno v: IEEE Journal of Solid-State Circuits. 55:693-705

This article presents a split time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) with digital background timing-skew mismatch calibration. It divides a TI-SAR ADC into two split parts with the same overall

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::893035a487f6e48be41b4f2b010b9dd2
https://doi.org/10.1109/jssc.2019.2945298

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Akademický článek

23 µW 8.9-effective number of bit 1.1 MS/s successive approximation register analog-to-digital converter with an energy-efficient digital-to-analog converter switching scheme

Autor: Lei Sun, Chi Tung Ko, Marco Ho, Wai Tung Ng, Ka Nang Leung, Chiu Sing Choy, Kong Pang Pun

Publikováno v: The Journal of Engineering (2014)

This study presents a successive approximation register analog-to-digital converter with an energy-efficient switching scheme. A split-most significant bit capacitor array is used with a least significant bit-down switching scheme. Compared with the

Externí odkaz: https://doaj.org/article/5ea125408e894d8285d5a446c876cf37

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An Input Frequency Insensitive Minimalism SAR with Semi-Synchronous Logic for Time-Interleaving Applications

Autor: Hong-bo Zhang, Ning Ding, Mu Yusong, Jiaqi Jiang, Yuchun Chang

Publikováno v: 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT).

This paper presents a 1b/cycle, 100-MS/s, 10-b, minimalism single-channel SAR ADC, featured with a 400-MHz effective resolution bandwidth (ERBW), which facilitates it to be embedded into time-interleaved applications. The limited rising time of track

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1af5f1318db0840c832d4c0201fc4374
https://doi.org/10.1109/icsict49897.2020.9278232

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A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS

Autor: Bo Wu, Yongda Cai, Shuang Zhu, Yun Chiu

Publikováno v: IEEE Journal of Solid-State Circuits. 53:1172-1183

A non-interleaved 2-GS/s, 8-bit flash analog-to-digital converter (ADC) utilizing the remainder number system (RNS) quantization principle is presented. The RNS quantization reduces the number of comparators and thus improves the figure of merit of t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3dd82d5d79947921b9b585c915c11501
https://doi.org/10.1109/jssc.2017.2774280

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An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS

Autor: Hae-Seung Lee, Xi Yang, Seung-Jun Bae

Publikováno v: ESSCIRC

An 8-bit 2.8 GS/s flash ADC with time-based offset calibration and interpolation is realized in 65 nm CMOS. The proposed time-based offset calibration uses intentional timing skew for offset cancellation without adding extra load to comparators, thus

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::40ad3579b197eabc0014da4c69530112
https://doi.org/10.1109/esscirc.2019.8902814

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A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS

Autor: Friedel Gerfers, Marcel Runge, Dario Schmeck, Georg Boeck, Philipp Scholz

Publikováno v: ESSCIRC

This paper presents the first published 9 bit resolution charge-injection cell based area-efficient SAR-ADC (ciSAR). The ciSAR employs both, a charge pump technique as well as a charge balancing switching scheme during binary search. Herewith, the ci

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3cdb277720e49554f80863e1f6740160
https://doi.org/10.1109/esscirc.2018.8494339

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