Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Edwin Thaller"'
Autor:
Mark Elzinga, Ashoke Ravi, Edwin Thaller, Rotem Banin, Run Levinger, Kamran Azadet, Christian Krassnitzer, Sergey Bershansky, Christoph Duller, Aryeh Farber, Jasmin Kadry, Gil Horovitz, Evgeny Shumaker, Patrick Torta, Nir Geron
Publikováno v:
ISSCC
The demand for massive MIMO, digital beamforming, and increased bandwidth communication dramatically increases the complexity of the remote radio head in future cellular base-stations. This complexity issue can be addressed by RF transceiver SoCs inc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c5554f8ca61da2352f595a435b9c4f1
https://doi.org/10.1109/isscc42613.2021.9365775
https://doi.org/10.1109/isscc42613.2021.9365775
Autor:
Edwin Thaller, Davide Ponton, Gerhard Knoblinger, Antonio Passamani, Andrea Bevilacqua, Andrea Neviani
Publikováno v:
ISSCC
In today's connected world, smaller and leaner wireless applications emerge, calling for increasingly higher integration and smaller footprint, while ensuring high reliability and operation at limited supply voltages. In this context, the integration
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::33b0b5283295f56303965a85fc7c9857
http://hdl.handle.net/11577/3227620
http://hdl.handle.net/11577/3227620
Publikováno v:
NEWCAS
This paper presents a novel method to digitally compensate the voltage ripple of a DC-DC switching converter supplying a Switched-Capacitor Power Amplifier (SCPA). Switched DC-DC converters are highly efficient, but their output voltage exhibits a sm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44d1fccd28404b6e86c66c9fa4d72cde
https://doi.org/10.1109/newcas.2016.7604749
https://doi.org/10.1109/newcas.2016.7604749
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:1482-1490
We present a low-jitter digital LC phase-locked loop (PLL) in a standard digital 130-nm CMOS technology, aiming at, but not limited to, clock multiplication in high-speed digital serial interface transceivers. The PLL features a fully digital core an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3faca289fd50535b82a8b1cc4d5deeb
https://doi.org/10.1109/jssc.2005.847325
https://doi.org/10.1109/jssc.2005.847325
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference.
A fully integrated digital LC PLL for low jitter frequency synthesis in a standard digital 130 nm CMOS technology is presented. The PLL features a fully digital core and a digitally controlled LC oscillator. It supports triple-band operation in multi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a378c148a4c5a6090f49005bc0b2fe7
https://doi.org/10.1109/esscir.2004.1356695
https://doi.org/10.1109/esscir.2004.1356695
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
A 13 GHz PLL designed for future WLAN systems in the 17 GHz ISM band includes a differentially tuned LC VCO, IQ-divider, 212-217 low power multi-modulus prescaler, differential phase-frequency detector, charge pump with loop filter, and a 2nd-order n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e56b27ec5370a219bc355573009f010b
https://doi.org/10.1109/isscc.2004.1332756
https://doi.org/10.1109/isscc.2004.1332756