Výsledky vyhledávání - "Edwin Rijpkema"

Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip

Autor: Andrei Radulescu, Edwin Rijpkema, J. van Meerbergen, John Dielissen, Kees Goossens, E. Waterlander, Paul Wielage

Publikováno v: IEE Proceedings. Part E, Computers and Digital Techniques, 150(5), 294-302. Institute of Electrical Engineers

Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as networks on chip (NoC), must be used. It is sho

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a44e224a2e6b0d1c979c30f30f070ca7
https://doi.org/10.1049/ip-cdt:20030830

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A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

Autor: Edwin Rijpkema, Andrei Radulescu, Om P. Gangwal, Kees Goossens, Santiago González Pestana, John Dielissen

Publikováno v: DATE

Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8fa6cf5b1772f9017c2c4537b339e27e
https://hal.archives-ouvertes.fr/hal-00181291

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Guaranteeing the Quality of Services in Networks on Chip

Autor: Andrei Radulescu, Peter Poplavko, Paul Wielage, E. Waterlander, Edwin Rijpkema, Kees Goossens, Jef van Meerbergen, John Dielissen

Publikováno v: Networks on Chip ISBN: 9781402073922
Networks on Chip

Users expect a predictable quality of service (QOS) of embedded systems, even for future, more dynamic, applications. System-on-chip designers use networks on chip (NOC) to solve deep submicron problems, and to divide global problems into local, deco

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3f34dae2c052dcbae6a40ee64231e188
https://doi.org/10.1007/0-306-48727-6_4

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High level modeling for parallel executions of nested loop algorithms

Autor: Ed F. Deprettere, P. Lieverse, Edwin Rijpkema, Bart Kienhuis

Publikováno v: ASAP

High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications (algorithms) and the implementations (architecture), a mapping of the former into the latter and a simulator for

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5eeee982c2c466dec1ce78cb3461087b
https://doi.org/10.1109/asap.2000.862380

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Compaan: deriving process networks from Matlab for embedded signal processing architectures

Autor: Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis

Publikováno v: CODES

This paper presents the Compaan tool that automatically transforms a nested loop program written in Matlab into a process network specification. The process network model of computation fits better with the new emerging kind of embedded architectures

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::601b0925abcfa20b9ee5a1e65064f325
https://doi.org/10.1109/hsc.2000.843699

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