Zobrazeno 1 - 10
of 127
pro vyhledávání: '"Edward S. Davidson"'
Publikováno v:
IEEE Transactions on Computers. 53:126-140
The growing difference between processor and main memory cycle time demands the use of aggressive prefetch algorithms to reduce the effective memory access latency. However, prefetching can significantly increase memory traffic and unsuccessful prefe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce527b2412e76eed41f736e6a10e9951
https://doi.org/10.1109/tc.2004.1261824
https://doi.org/10.1109/tc.2004.1261824
Publikováno v:
HPCA
With the continuing technological trend of ever cheaper and larger memory, most data sets in database servers will soon be able to reside in main memory. In this configuration, the performance bottleneck is likely to be the gap between the processing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eb208a827423a8b08b424852169cfde5
https://doi.org/10.1145/945506.945509
https://doi.org/10.1145/945506.945509
Publikováno v:
International Conference on Supercomputing
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c82e495f9546a9d30edcbc74ef589d2b
https://doi.org/10.1145/2591635.2667171
https://doi.org/10.1145/2591635.2667171
Publikováno v:
ICS 25th Anniversary
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9135260d802b67bfe2c0ea95508de1be
https://doi.org/10.1145/2591635.2591653
https://doi.org/10.1145/2591635.2591653
Publikováno v:
ISCA
Data cache misses reduce the performance of wide-issue processors by stalling the data supply to the processor. Prefetching data by predicting the miss address is one way to tolerate the cache miss latencies. But current applications with irregular a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::af3ec0993b7940b099b92c349e113d65
https://doi.org/10.1145/384285.379251
https://doi.org/10.1145/384285.379251
Publikováno v:
IEEE Transactions on Computers. 50:769-783
In this paper, we examine the effectiveness of a new hardware mechanism, called register queues (RQs), which effectively decouples the architected register space from the physical registers. Using RQs, the compiler can allocate physical registers to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::88440a06e048055ed19caf24997e8202
https://doi.org/10.1109/12.946998
https://doi.org/10.1109/12.946998
Publikováno v:
IEEE Transactions on Computers. 48:1244-1259
As microprocessor speeds continue to outpace memory subsystems in speed, minimizing average data access time grows in importance. Multilateral caches afford an opportunity to reduce the average data access time by active management of block allocatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00be5a442ba415dcd81461d94a042258
https://doi.org/10.1109/12.811113
https://doi.org/10.1109/12.811113
Autor:
Gheith A. Abandah, Edward S. Davidson
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 9:206-216
In a distributed shared memory (DSM) multiprocessor, the processors cooperate in solving a parallel application by accessing the shared memory. The latency of a memory access depends on several factors, including the distance to the nearest valid dat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb4e19598a612085b551542254519927
https://doi.org/10.1109/71.663946
https://doi.org/10.1109/71.663946
Publikováno v:
PLDI
Modulo scheduling algorithms based on optimal solvers have been proposed to investigate and tune the performance of modulo scheduling heuristics. While recent advances have broadened the scope for which the optimal approach is applicable, this approa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::584a534dd16004a4ae5d149c5f4807b2
https://doi.org/10.1145/258916.258933
https://doi.org/10.1145/258916.258933
Autor:
Jude A. Rivers, Edward S. Davidson
Publikováno v:
Performance Evaluation. :189-207
This work evaluates the performance effectiveness of combining two techniques for improving cache hit rate and reducing memory traffic in small on-chip direct-mapped caches. Temporality-based caching is an efficient technique for reducing unnecessary
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9b75d802c8093b5cbbd969d5faad37ee
https://doi.org/10.1016/0166-5316(96)00037-5
https://doi.org/10.1016/0166-5316(96)00037-5