Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Edward O. Travis"'
Publikováno v:
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films. 11:1692-1695
We report for the first time the characteristics of the early growth of chemical vapor deposition (CVD) TiN films on Si (100) in the surface reaction limited regime, using total reflection x‐ray fluorescence (TXRF), atomic force microscopy (AFM), a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::31ee2c46d777e8cc9f6bff9aeaccc09b
https://doi.org/10.1116/1.578480
https://doi.org/10.1116/1.578480
Autor:
E. Luckowski, M. Celik, M. Raymond, Byoung W. Min, B. Melnick, Hector Sanchez, D. Spilo, Ana Olivia Ruíz Martínez, W. Johnstone, Pak K. Leung, C. Happ, D. Goedeke, D. Roberts, J. Hayden, T. Remmel, Edward O. Travis, O.P. Mandhana, J. Edgerton, B. Wilson, K. Ramakrishna, T. Garnett, B. E. White
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
A reliable metal-insulator-metal (MIM) capacitor exceeding 250nF has been integrated into the copper/low-K backend of a high-performance 90nm SOI technology. The reduction of supply grid voltage transients has enhanced microprocessor performance by a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff1c26abafb45fcb60b8393c70add531
https://doi.org/10.1109/iedm.2005.1609269
https://doi.org/10.1109/iedm.2005.1609269
Publikováno v:
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
This paper presents a new two-dimensional (2-D) low pass filter model for the prediction of post-chemical-mechanical polishing (CMP) die level wafer topography variation caused by the interconnect metal density of a circuit layout. It is demonstrated
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49eab1a87286a8d9f6fe4fd3a6044b18
https://doi.org/10.1109/iedm.1999.824296
https://doi.org/10.1109/iedm.1999.824296
Autor:
L. Pressley, R. Nelson, D. Menke, D. Farber, S. Chheda, P. Crabtree, Suresh Venkatesan, Martin Gall, R. Islam, S. Blackley, Charles Fredrick King, T. Sparks, Tab A. Stephens, Russell L. Carter, D. Jawarani, David Smith, B. Smith, Edward O. Travis
Publikováno v:
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).
A comparison of via overetch is made between a conventional integration using aluminum interconnects plus tungsten via plugs and a dual-inlaid integration using copper. Excessive overetch for Al interconnects can cause reliability problems because of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26324450900bd4ad8250b7f7a9eb3bc0
https://doi.org/10.1109/iitc.1999.787092
https://doi.org/10.1109/iitc.1999.787092
Autor:
B. Anthony, Edward O. Travis, S. Poon, S. Mattay, I. Yang, A. Perera, Navakanta Bhat, T. Vuong, A. Nagy, A. Kaiser, M. Schippers, B. Kruth, S. Venkatesan, S. Chheda, J. Porter, T. Lii, H. Chuang, Veena Misra, Percy V. Gilbert, J. West, Ted R. White, P. Chen, Paul G. Y. Tsui, John M. Grant
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
A modular 0.25 /spl mu/m CMOS core technology suitable for high density and high-performance or low-power applications is presented. The key salient features include: simple 1-mask STI, 40 /spl Aring/ high-performance or low-power CMOS transistor mod
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84df5f476a5f2c37a4ec57691970de03
https://doi.org/10.1109/vlsit.1998.689237
https://doi.org/10.1109/vlsit.1998.689237
Autor:
M. Kling, W. Grobman, K. Lucas, Percy V. Gilbert, B. Roman, Edward O. Travis, J. West, T. Vuong, Paul G. Y. Tsui, H. Chuang, K. Reich
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of-the-art 0.25 /spl mu/m random logic process in order to reduce metal line pullback on critical layers. The techniques used are ru
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ebdfae34477a220e4e2c194292dc700
https://doi.org/10.1109/iedm.1997.650429
https://doi.org/10.1109/iedm.1997.650429
Autor:
Kathleen A. Perry, Bich-Yen Nguyen, T. Saaranen, Matthew A. Thompson, Stanley M. Filipiak, L.B. La, Edward O. Travis, A.V. Gelatos, Navakanta Bhat, Phil Tobin, J. Peschke, R. Marsh
Publikováno v:
1995 Symposium on VLSI Technology. Digest of Technical Papers.
The report describes the integration of copper into the backend of a two-level metal 0.5 /spl mu/m BiCMOS SRAM circuit. The circuit is used to evaluate the impact of copper on the device characteristics. The results of time dependent gate dielectric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::60ef79704298420c92400aa23570fa14
https://doi.org/10.1109/vlsit.1995.520842
https://doi.org/10.1109/vlsit.1995.520842
Publikováno v:
Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).
In a trench-first-via-last (TFVL) dual-inlaid metal process, the thickness of resist coated in the via definition step after trench formation varies according to underlying trench topography. Variation in resist thickness reduces via size uniformity
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1d9942d284f5c1664e20bf440b567bf
https://doi.org/10.1109/iitc.2001.930013
https://doi.org/10.1109/iitc.2001.930013
Autor:
Warren D. Grobman, Paul G. Y. Tsui, Edward O. Travis, Kevin D. Lucas, Alfred J. Reich, Tam Vuong, Michael E. Kling, Percy V. Gilbert, H. Chuang, Jeff P. West, Bernard J. Roman
Publikováno v:
SPIE Proceedings.
Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a0bbd340f655f0afb477edb6c6ffca2
https://doi.org/10.1117/12.310749
https://doi.org/10.1117/12.310749
Autor:
Edward O. Travis, Stanley M. Filipiak, C. J. Mogab, Matthew A. Thompson, Bich-Yen Nguyen, Phil Tobin, T. Saaranen, R. Marsh, J. Peschke, Avgerinos V. Gelatos, Kathleen A. Perry
Publikováno v:
SPIE Proceedings.
Continued dimensional scaling of the elements of integrated circuits places significant restrictions on the width, density and current carrying capability of metallic interconnects. It is expected that, by the year 2000, the transistor channel length
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3347f03ef65c75f3fd59eda056d4c58
https://doi.org/10.1117/12.250884
https://doi.org/10.1117/12.250884