Zobrazeno 1 - 10
of 77
pro vyhledávání: '"Eduardo Peralias"'
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 68:3197-3210
This paper presents a novel Look-up Table (LUT) calibration technique for static non-linearity compensation in analog-to-digital converters (ADCs) with digital redundancy, such as Successive Approximation Register (SAR), Algorithmic, Sub-ranging or P
Publikováno v:
Digital.CSIC. Repositorio Institucional del CSIC
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This paper presents a simple but accurate normalized nonlinear large-signal semiempirical MOS transistor model to be used in monolithic RF Class A-to-C PAs. MOS transistor characteristics, saved in lookup tables, are extracted for different PVT corne
Publikováno v:
International Journal of Circuit Theory and Applications. 47:333-349
Publikováno v:
ISCAS
This paper presents a robust method to perform capacitor mismatch calibration in a redundant SAR ADCs correcting the effect of comparator static offset in the calibration process. Without proper handling of this effect, capacitor miscalibration can o
Publikováno v:
ISCAS
This paper presents a new simulation method for fast evaluation of non-linear circuits. The proposed approach solves the non-linear ordinary differential equation (ODE) set of the system using a semi-analytical solution based on the matrix exponentia
Publikováno v:
NEWCAS
This paper presents a digital non-linear calibration technique for Pipeline ADCs using a novel Look-up Table (LUT) approach. Due to redundancy, the signal paths (and hence, the errors in Pipeline ADCs) are not unique for a given input level. This eff
Publikováno v:
NEWCAS
This work introduces a digital technique to measure and correct the mismatch between capacitors in SAR ADCs with split capacitor-based DAC (CDAC), including the bridge capacitor impairments. The method takes advantage of redundancy for calibration wi
Publikováno v:
DCIS
This paper presents a robust method to perform capacitor mismatch calibration in a redundant SAR ADCs correcting the effect of comparator static offset in the calibration process. Without proper handling of this effect, capacitor miscalibration can o
Publikováno v:
Digital.CSIC. Repositorio Institucional del CSIC
instname
instname
This brief presents a digital calibration technique for compensating timing-skew errors between the sub-ADC and the MDAC in the first stage of sample-and-hold amplifier (SHA)-less pipeline ADCs. In the presence of clock-skew errors, sub-ADC comparato
Publikováno v:
idUS. Depósito de Investigación de la Universidad de Sevilla
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Digital.CSIC. Repositorio Institucional del CSIC
instname
Digital.CSIC. Repositorio Institucional del CSIC
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (