Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Edmund Blackshear"'
Autor:
Zhi Yang, David B. Stone, Janak G. Patel, Kwang Won Choi, Eric W. Tremble, Edmund Blackshear, Kathryn C. Rivera
Publikováno v:
International Symposium on Microelectronics. 2019:000120-000126
Laminates or sequential build-up (SBU) laminate comprised of dielectric materials, metal traces, and metal vias not only serve as the mechanical support for the silicon integrated circuits (ICs), but also electrically connect ICs to ball grid array (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01baaa429aa93f2bdfc6b8dc1e58c71c
https://doi.org/10.4071/2380-4505-2019.1.000120
https://doi.org/10.4071/2380-4505-2019.1.000120
Autor:
Kwang Won Choi, Keiichi Hirabayashi, Edmund Blackshear, Jean Audet, David B. Stone, Eric W. Tremble
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
High speed SerDes standards demand higher speed signals for the next generation - 112Gbit/sec. The integrity of signals is affected strongly by the physical characteristics of the printed circuit substrate in a 112Gbit/s high speed device. The effect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e556af581802a5051e916c24c71fa648
https://doi.org/10.1109/ectc.2019.00183
https://doi.org/10.1109/ectc.2019.00183
Autor:
David Questad, Edmund Blackshear, Manish Nayini, Charles Carey, Zhuo-Jie Wu, Donovan Samantha
Publikováno v:
IRPS
This paper reports a comprehensive CPI study of a large die in 5 different flip chip packaging configurations. Chip corner crack and delamination were observed in temperature cycling stresses. Kerf size effect and substrate effect were studied in det
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4190ae3655fa84b8e8c76ca488bfd2e
https://doi.org/10.1109/irps.2019.8720530
https://doi.org/10.1109/irps.2019.8720530
Autor:
Edmund Blackshear, Benjamin V. Fasano, Brian W. Quinlan, Yoichi Miyazawa, Tomoyuki Yamada, Richard Alan Heath, Paul Fortier, Frederick H. Roy, Hugues C Gagnon, David J. Lewison, Itsuroh Shishido, Elaine Cyr Takashi Nakajima, Shidong Li
Publikováno v:
International Symposium on Microelectronics. 2014:000074-000080
Coreless flip chip laminate substrates have shown significant advantages over cored versions in terms of wireability due to the absence of large coarse pitch core vias and accompanying via lands. Resistance to widespread acceptance of coreless has be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18cd8e5125bf230ff5e5684d993d2d01
https://doi.org/10.4071/isom-ta32
https://doi.org/10.4071/isom-ta32
Publikováno v:
ECS Transactions. 18:701-706
Server system requirement drives the evolution of 3D DRAM technologies. The new generation provides form factor, electrical and power performance benefits. Meanwhile it brings in a more complicated design, new assembly technologies and new failure me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01ed96580d903d30d33e4f55af618026
https://doi.org/10.1149/1.3096524
https://doi.org/10.1149/1.3096524
Autor:
D.N. de Araujo, Jamil A. Wakil, Stefano S. Oggioni, Edmund Blackshear, Ronald S Malfatt, S. R. Engle, Gareth G. Hougham, E. Klink, Moises Cases, David J. Russell, L. D. LaCroix, Nam H. Pham
Publikováno v:
IBM Journal of Research and Development. 49:641-661
This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988. It reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structure
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99437c0b2e82e017a0453474151ad61a
https://doi.org/10.1147/rd.494.0641
https://doi.org/10.1147/rd.494.0641
Autor:
Mantilla Oswald J, Marcus E. Interrante, Edmund Blackshear, Katsuyuki Sakuma, Jae-Woong Nah, Chenzhou Lian, Tunga Krishna R, Shidong Li
Publikováno v:
2013 IEEE 63rd Electronic Components and Technology Conference.
In this work, differential heating/cooling chip join process was developed for coreless flip chip packaging to minimize warpage change of coreless substrates during the bonding process. A chip was vacuumed to a bonder head and a coreless substrate wa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b30ba13383ae2902784accdedb02330
https://doi.org/10.1109/ectc.2013.6575645
https://doi.org/10.1109/ectc.2013.6575645
Autor:
Frank L. Pompeo, Thomas E. Lombardi, Edmund Blackshear, JoonYeob Lee, Joonyoung Choi, KyungMooon Kim, Jean Audet, Kyoji Kondo, ChangWoo Park, Yoichi Miyazawa, Shunichiro Matsumoto, YoungHyuk Jeong
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
The trend in large body, high performance integrated circuit packaging for the 32 nm semiconductor node and beyond is towards low dielectric loss to enable high bandwidth / low loss channels, and low thermal expansion to protect fragile, ultra-low di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::43b24a18002c05e1e333c93097e591d0
https://doi.org/10.1109/ectc.2011.5898561
https://doi.org/10.1109/ectc.2011.5898561