Zobrazeno 1 - 10
of 346
pro vyhledávání: '"Earl E. Swartzlander"'
Publikováno v:
2022 IEEE Radiation Effects Data Workshop (REDW) (in conjunction with 2022 NSREC).
Autor:
Earl E. Swartzlander, Chenghua Wang, Peipei Yin, Yuying Zhu, Weiqiang Liu, Cao Tian, Fabrizio Lombardi
Publikováno v:
IEEE Transactions on Computers. 68:804-819
As technology scaling is reaching its limits, new approaches have been proposed for computional efficiency. Approximate computing is a promising technique for high performance and low power circuits as used in error-tolerant applications. Among appro
Publikováno v:
UEMCON
This paper describes a new floating-point fused multiplier-adder (FMA) designed for bfloat16 data. Analysis and optimizations for 8-bit exponent logic, adders, and multiplier are presented, and compared in performance and area against a double-precis
Publikováno v:
Liu, W, Mei, F, Wang, C, O'Neill, M & Swartzlander, E E 2018, ' Data Compression Device based on Modified LZ4 Algorithm ', IEEE Transactions on Consumer Electronics, vol. 64, no. 1, pp. 110-117 . https://doi.org/10.1109/TCE.2018.2810480
Data compression is commonly used in NAND flash-based solid state drives (SSDs) to increase their storage performance and lifetime as it can reduce the amount of data written to and read from NAND flash memory. Software-based data compression reduces
Publikováno v:
IEEE Transactions on Computers. 66:1994-2004
A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS)
Publikováno v:
Journal of Signal Processing Systems. 90:641-654
Approximate/inexact computing has become an attractive approach for designing high performance and low power arithmetic circuits. Floating-point (FLP) arithmetic is required in many applications, such as digital signal processing, image processing an
Autor:
Yao-Feng Chang, Burt Fowler, Ying-Chen Chen, Earl E. Swartzlander, Lauren Guckert, Fei Zhou, Jack C. Lee, Cheng-Chih Hsieh
Publikováno v:
IEEE Transactions on Electron Devices. 64:2977-2983
In this paper, implication (IMP) operations are demonstrated in a circuit with two SiOx-based memristors and a CMOS transistor. Specifically, a circuit with two one-diode and one-resistor (1D1R) memory elements and a transistor are designed to perfor
Publikováno v:
Journal of Signal Processing Systems. 90:409-419
In this paper, hybrid parallel-prefix/carry select and skip adder (PPF/CSSA) schemes are proposed for high-speed wide-size adders. The proposed adders are based on an improved design of the parallel-prefix network and carry select (CSL) blocks. In th
Autor:
Lauren Guckert, Earl E. Swartzlander
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 64:171-175
Memristors have recently begun to be explored in arithmetic applications. However, all prior designs for memristor-based gates have had shortcomings in terms of scalability, applicability, completeness, and performance. In this brief, a new low-power
Autor:
Earl E. Swartzlander, Lauren Guckert
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 64:373-385
Since memristors came to the forefront of research, minimal work has explored their application to computer arithmetic. This paper proposes two memristor-based implementations of an N-bit shift-and-add multiplier, one using IMPLY operations and a sec