Zobrazeno 1 - 10
of 64
pro vyhledávání: '"E.F. Haratsch"'
Publikováno v:
IEEE Transactions on Magnetics. 46:933-941
We report on the use of low-density parity check (LDPC)-centric error correction coding (ECC) for magnetic recording read channel in the presence of significant burst errors. Since an LDPC code by itself is severely vulnerable to burst errors due to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d766cb9f4f6ddd8c5f6643d91aa317eb
https://doi.org/10.1109/tmag.2009.2034012
https://doi.org/10.1109/tmag.2009.2034012
Publikováno v:
IEEE Transactions on Magnetics. 46:87-91
Although the performance of a magnetic recording read channel can be improved by employing advanced iterative signal detection and coding techniques, the method nevertheless tends to incur significant silicon area and energy consumption overhead. Mot
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::371e7ed510e85cca76df71d683b706b6
https://doi.org/10.1109/tmag.2009.2026898
https://doi.org/10.1109/tmag.2009.2026898
Publikováno v:
IEEE Transactions on Magnetics. 44:4784-4789
In this paper, we examine the potential of applying concatenated low-density parity-check (LDPC) and Bose-Chaudhuri-Hocquenghem (BCH) coding for magnetic recording read channel with a 4 kB sector format. One key observation for such concatenated codi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21560e31088fa477e3537a4ccda0993e
https://doi.org/10.1109/tmag.2008.2004380
https://doi.org/10.1109/tmag.2008.2004380
Publikováno v:
IEEE Transactions on Magnetics. 43:1118-1123
By implementing a field-programmable gate array (FPGA)-based simulator, we investigate the performance of randomly constructed high-rate quasi-cyclic (QC) low-density parity-check (LDPC) codes for the magnetic recording channel at very low block sect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13e07d4d15b4f19026594e3aec7f68ac
https://doi.org/10.1109/tmag.2006.888607
https://doi.org/10.1109/tmag.2006.888607
Autor:
M.S. Shaffer, Fadi Saibi, Kamran Azadet, H. Kim, Meng-Lin Yu, J.H. Saunders, E.F. Haratsch, Leilei Song
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:317-327
In this tutorial paper, we present the application of well-known DSP techniques used in lower speed wireline and wireless applications, to high-speed optical communications. After an introduction on today's optical network architecture and typical op
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb266da4c432fe270bde5694dfad2456
https://doi.org/10.1109/4.987083
https://doi.org/10.1109/4.987083
Autor:
K. Azadet, E.F. Haratsch
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:374-384
1000BASE-T Gigabit Ethernet employs eight-state 4-dimensional trellis-coded modulation to achieve robust 1-Gb/s transmission over four pairs of Category-5 copper cabling. This paper compares several postcursor equalization and trellis decoding algori
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89f17106ea3859e06f81667f165817e4
https://doi.org/10.1109/4.910476
https://doi.org/10.1109/4.910476
Autor:
E.F. Haratsch, K.K. Fitzpatrick
Publikováno v:
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
A new radix-4 soft-output Viterbi architecture is presented, which achieves higher data rates than prior radix-2 SOVA designs. The proposed architecture is also more hardware-efficient than a previously reported radix-4 SOVA architecture. New circuit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d1ae495d0816423f3460f9c964299b0
https://doi.org/10.1109/vdat.2008.4542453
https://doi.org/10.1109/vdat.2008.4542453
Publikováno v:
GLOBECOM
A bit-node centric decoder architecture for low- density parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processing unit computes the bit-to-check node messages sequentially, while the computat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d769f9fe717c232a74a4265d0df132e
https://doi.org/10.1109/glocom.2007.57
https://doi.org/10.1109/glocom.2007.57
Publikováno v:
ICCCN
A serial sum-product architecture for low-density parity-check (LDPC) codes is presented. In the proposed architecture, a standard bit node processing unit computes the bit to check node messages sequentially, while the check node computations are br
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e66ba505e707be6999dce575845aeac4
https://doi.org/10.1109/icccn.2007.4317812
https://doi.org/10.1109/icccn.2007.4317812
Publikováno v:
ISCAS
By implementing an FPGA-based simulator, we investigate the performance of high-rate quasi-cyclic (QC) LDPC codes for the magnetic recording channel at very low sector error rates. Results show that error-floor-free performance can be realized by ran
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::37d2474cf9ca97de9e1624d4f1a1fceb
https://doi.org/10.1109/iscas.2006.1693392
https://doi.org/10.1109/iscas.2006.1693392