Zobrazeno 1 - 10
of 336
pro vyhledávání: '"E.E. Swartzlander"'
Autor:
Sungwook Yu, E.E. Swartzlander
Publikováno v:
IEEE Transactions on Signal Processing. 50:160-167
This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12e7600fa3f8b6d6293751076802ad5a
https://doi.org/10.1109/78.972492
https://doi.org/10.1109/78.972492
Autor:
E.E. Swartzlander, Sungwook Yu
Publikováno v:
IEEE Transactions on Signal Processing. 49:2096-2102
This paper presents an efficient pipelined architecture for the N/sup m/-point m-dimensional discrete Fourier transform (DFT). By using a two-level index mapping scheme that is different from the conventional decimation-in-time (DIT) or decimation-in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b61ca0486b860a715ecb90da0bbe281
https://doi.org/10.1109/78.942637
https://doi.org/10.1109/78.942637
Autor:
Jr. E.E. Swartzlander
Publikováno v:
IEEE Design & Test of Computers. 15:28-34
Three IC technologies result in different outcomes-performance and cost-in two case studies. The author compares their designs in terms of silicon area, substrate size, and power consumption.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::256d69e091d287db31389012d8e0ce34
https://doi.org/10.1109/54.706030
https://doi.org/10.1109/54.706030
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1:164-167
It is shown that when the standard Booth multiplication algorithm is extended to higher radix (>2) fixed-point multiplication, incorrect results are produced for some word sizes. A rule which modifies the algorithm to correct this problem is presente
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bbaa4c081e6c3631c3d8fd87501a7119
https://doi.org/10.1109/92.238420
https://doi.org/10.1109/92.238420
Autor:
null Heumpil Cho, E.E. Swartzlander
Publikováno v:
2006 Sixth IEEE Conference on Nanotechnology.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d49625ced7ca19d0ac340fbb6dae05e4
https://doi.org/10.1109/nano.2006.1717102
https://doi.org/10.1109/nano.2006.1717102
Autor:
M.O. Sanu, E.E. Swartzlander
Publikováno v:
ASAP
Finite field arithmetic is useful in the implementation of error-correcting codes as well as cryptographic protocols. Large finite field numbers are particularly important in the implementation of elliptic curve cryptography. This paper presents a mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cdf20994010294a0acb45799afa7490
https://doi.org/10.1109/asap.2005.46
https://doi.org/10.1109/asap.2005.46
Publikováno v:
Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..
Multiprecision multipliers reduce power consump- tion by selecting smaller multipliers (i.e., submultiplier) according to the wordsize of the input operands. However, arbitrary levels of bit precision are not achieved by multiprecision multipliers. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ebc96ff15ac33be84f402df12f1f2752
https://doi.org/10.1109/acssc.2005.1600041
https://doi.org/10.1109/acssc.2005.1600041
Autor:
M.O. Sanu, E.E. Swartzlander
Publikováno v:
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..
In this paper, we describe a novel algorithm for modular exponentiation of large integers and present its hardware implementation. This algorithm combines elements from Montgomery's modular multiplication technique, carry-save and carry-delayed numbe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00a78f62b61ef4cdd1355e6f77026cb2
https://doi.org/10.1109/sips.2005.1579840
https://doi.org/10.1109/sips.2005.1579840
Publikováno v:
2003 46th Midwest Symposium on Circuits and Systems.
A new digital background calibration technique for pipelined analog-to-digital converter (ADC) is proposed in this paper. In this architecture, two redundant pipelined stages are added to the ADC that creates time slots for the pipelined stages such
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cdf217e76497ea4f905a65f081cfe589
https://doi.org/10.1109/mwscas.2003.1562205
https://doi.org/10.1109/mwscas.2003.1562205
Autor:
I.H. Unwala, E.E. Swartzlander
Publikováno v:
1993 IEEE International Symposium on Circuits and Systems.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d7565687ee29aa2597fec49c06f9d030
https://doi.org/10.1109/iscas.1993.693030
https://doi.org/10.1109/iscas.1993.693030