Zobrazeno 1 - 10
of 24
pro vyhledávání: '"E. Baylac"'
Autor:
Didier Dutartre, Sylvie Ortolland, Michel Haond, Emmanuel Josse, Francois Andrieu, R. Nicolas, Alain Claverie, Thierry Poiroux, E. Baylac, R. Berthelon
Publikováno v:
Solid-State Electronics
Solid-State Electronics, 2017, 128, pp.72-79. ⟨10.1016/j.sse.2016.10.011⟩
Solid-State Electronics, Elsevier, 2017, 128, pp.72-79. ⟨10.1016/j.sse.2016.10.011⟩
Solid-State Electronics, 2017, 128, pp.72-79. ⟨10.1016/j.sse.2016.10.011⟩
Solid-State Electronics, Elsevier, 2017, 128, pp.72-79. ⟨10.1016/j.sse.2016.10.011⟩
The introduction of strained channel is mandatory to achieve high performance in Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI) technology. Especially, compressive SiGe channel has been demonstrated to enhance hole
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2be0fe58898ee72276d44b6166cc9b83
https://doi.org/10.1016/j.sse.2016.10.011
https://doi.org/10.1016/j.sse.2016.10.011
Autor:
Simeon Morvan, E. Baylac, Emmanuel Josse, Michel Haond, Cyrille Le Royer, Olivier Gourhant, Didier Dutartre, Remy Berthelon, Francois Andrieu
Publikováno v:
ECS Transactions. 75:3-14
We have physically and electrically characterized pMOSFETs of compressively strained SiGe channel built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). Such a channel greatly contributes to the FDSOI CMOS high-pe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::992c2bb266222df76b2640ebe97cae29
https://doi.org/10.1149/07508.0003ecst
https://doi.org/10.1149/07508.0003ecst
Autor:
Charles Baudot, E. Baylac, Nathalie Vulliet, Sebastien Cremer, Frederic Boeuf, S. Messaoudene
Publikováno v:
ECOC
In this paper we discuss the specific challenges of process integration of Si-Photonics for the current and future applications, including lithography, etching and heterogeneous materials integration.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3be8bafe63cd9272f05310e7493eff45
https://doi.org/10.1109/ecoc.2017.8346203
https://doi.org/10.1109/ecoc.2017.8346203
Autor:
F. Abbate, E Baylac, Clement Pribat, D. Barge, Marc Juhel, C. Gaumer, A. Pofelski, Vincent Mazzocchi, Germain Serventon, Olivier Gourhant, Francois Andrieu, Maud Bidaud
Publikováno v:
ECS Transactions. 64:469-478
High mobility channels are considered as an interesting path to increase PMOS performances for advanced CMOS technology. Silicon-Germanium On Insulator (SGOI) benefits from both the advantage of the SiGe material (hole mobility booster) and the On In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a8deae467a2adb71279cd274bc116fc8
https://doi.org/10.1149/06406.0469ecst
https://doi.org/10.1149/06406.0469ecst
Autor:
D. Barge, Thibaud Denneulin, C. Le Royer, David Cooper, Jean-Paul Barnes, P. Nguyen, O. Bonnin, J. M. Pedini, Olivier Gourhant, E. Baylac, Walter Schwarzenbach, Yves Campidelli, F. Glowacki, Y. Morand, Jean-Michel Hartmann, Denis Rouchon
Publikováno v:
Solid-State Electronics. 97:82-87
300 mm ultrathin Silicon-On-Insulator (SOI) wafers with SiGe/Si stacks on top were used as pre-structures for the fabrication of 5 nm thick SiGe-On-Insulator (SGOI) substrates obtained by the Ge enrichment technique. Those substrates will be used as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19b1ec5e7275fcbef97299a0ef893e41
https://doi.org/10.1016/j.sse.2014.04.026
https://doi.org/10.1016/j.sse.2014.04.026
Autor:
Michel Haond, Maud Vinet, Alain Aurand, V. Farys, E. Baylac, A. Claverie, E. Petitprez, Emmanuel Josse, Raphael Bingert, M-A. Jaud, T. Poiroux, E. Bechet, Jean-Claude Marin, Didier Dutartre, S. Delmedico, Olivier Weber, C. Bernicot, E. Bernard, P. Sardin, F Andrieu, S. Ortolland, Joris Lacord, E. Serret, R. Berthelon, Patrick Scheer, A. Pofelski, Pierre Perreau, Denis Rideau
Publikováno v:
VLSI Technology, 2016 IEEE Symposium on
VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573425⟩
2016 IEEE Symposium on VLSI Technology
VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573425⟩
2016 IEEE Symposium on VLSI Technology
cited By 4; International audience; We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bb1321d14ae9eb2e1bfa303be111c6af
https://doi.org/10.1109/vlsit.2016.7573425
https://doi.org/10.1109/vlsit.2016.7573425
Autor:
S. Ortolland, Michel Haond, E. Baylac, Thierry Poiroux, Didier Dutartre, Emmanuel Josse, R. Nicolas, R. Berthelon, Francois Andrieu, Alain Claverie
Publikováno v:
Ultimate Integration on Silicon (EUROSOI-ULIS), 2016 Joint International EUROSOI Workshop and International Conference on
Ultimate Integration on Silicon (EUROSOI-ULIS), 2016 Joint International EUROSOI Workshop and International Conference on, 2016, Unknown, Unknown Region. pp.88-91, ⟨10.1109/ULIS.2016.7440059⟩
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
Ultimate Integration on Silicon (EUROSOI-ULIS), 2016 Joint International EUROSOI Workshop and International Conference on, 2016, Unknown, Unknown Region. pp.88-91, ⟨10.1109/ULIS.2016.7440059⟩
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
cited By 3; International audience; The introduction of SiGe channel for pMOSFETs in FDSOI technology enables to achieve high performance. However, it has been demonstrated that such a global stressor induces layouts effects. In this paper, we presen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::533e905010b58daff2e208756b235be9
https://hal.archives-ouvertes.fr/hal-01719488
https://hal.archives-ouvertes.fr/hal-01719488
Autor:
Pierre Perreau, Michel Haond, Didier Dutartre, R Berthelon, Alain Claverie, A. Pofelski, Emmanuel Josse, Francois Andrieu, E. Baylac
Publikováno v:
Solid-State Device Research Conference (ESSDERC), 2016 46th European
Solid-State Device Research Conference (ESSDERC), 2016 46th European, 2016, Unknown, Unknown Region. pp.127-130, ⟨10.1109/ESSDERC.2016.7599604⟩
2016 46th European Solid-State Device Research Conference (ESSDERC)
ESSDERC
Solid-State Device Research Conference (ESSDERC), 2016 46th European, 2016, Unknown, Unknown Region. pp.127-130, ⟨10.1109/ESSDERC.2016.7599604⟩
2016 46th European Solid-State Device Research Conference (ESSDERC)
ESSDERC
cited By 0; International audience; We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::74f99594e3eba1ef53825f4f7cfb81a4
https://hal.science/hal-01719492
https://hal.science/hal-01719492
Autor:
B. Le-Gratiet, G. Druais, Denis Rideau, Marie-Anne Jaud, J.-D. Chapon, D. Hoguet, M. Mellier, L. Babaud, Clement Pribat, Emmanuel Josse, D. Barge, S. Puget, J. Mazurier, L. Grenouillet, Nicolas Loubet, S. Zoll, Thierry Poiroux, Jerome Simon, S.P. Fetterolf, M. Bidaud, S. Chhun, M. Vinet, Quanwei Liu, R. Bianchini, E. Bernard, J.-F. Kruck, X. Gerard, C. Gaumer, A. Pofelski, Francois Andrieu, Mustapha Rafik, Olivier Weber, N. Guillot, Pascal Gouraud, F. Abbate, O. Faynot, N. Degors, Olivier Gourhant, Antoine Cros, L. Parmigiani, E. Petitprez, J. Lacord, Patrick Scheer, C. Monget, Michel Haond, Evelyne Richard, P. Maury, Bruce B. Doris, M. Celik, Daniel Benoit, Frederic Monsieur, E. Baylac, L. Clément, S. Lagrasta, Magali Gregoire, J.-P. Manceau, S. Lasserre, P. Perreau, P. Brun, C. Gallon, V. Beugin, Remi Beneyton, Eric Perrin, S. Delmedico, R. Bingert
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 3
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aedffd54e01f33ec4661fa88cc9e090c
https://doi.org/10.1109/vlsit.2014.6894343
https://doi.org/10.1109/vlsit.2014.6894343
Autor:
N. Cave, Vincent Huard, C. Monget, C. Le Cam, S. Zoll, S. Parihar, S. Bordez, F. Guyader, D. Delille, N. Auriac, Michel Haond, R. Pantel, B. Icard, M. Zaleski, S. Harrison, A. Margain, C. Blanc, Scott Warrick, D. Barge, J. Belledent, D. Villanueva, Francois Leverd, G. Ribes, E. Baylac, Alexis Farcy, C. Laviron, Kathy Barla, E. Perrin, K. Rochereau, M. Bidaud, S. Manakli, Pascal Gouraud, Laurent Pain, O. Callen, Blandine Minghetti, Emmanuel Josse, Paulo Ferreira, R. Ranica
Publikováno v:
2006 International Electron Devices Meeting.
This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd04a63739424f6f3bc7798a8d44e368
https://doi.org/10.1109/iedm.2006.346880
https://doi.org/10.1109/iedm.2006.346880