Zobrazeno 1 - 10
of 47
pro vyhledávání: '"E J Nowak"'
Autor:
Gregory G. Freeman, E. J. Nowak, L. Sigal, Daniel J. Poindexter, Narasimha Rao Mavilla, C-H. Lin, Mohit Bajaj, Suresh Gundapaneni, James D. Warnock, Steven W. Mittl, Richard A. Wachnik, C. Scott, Noah Zamdmer, Paul S. McLaughlin, Siyuranga O. Koswatta, Sungjae Lee, J. Johnson
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM).
In this paper we show that devices in scaled technologies could undergo self-heating (SH) even in the off-state when subjected to stress conditions that would in turn adversely impact product life-time. We present a detailed methodology in analyzing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0484137733726941aea4a283056a8530
https://doi.org/10.1109/iedm.2015.7409740
https://doi.org/10.1109/iedm.2015.7409740
Autor:
Noah Zamdmer, Josef S. Watts, Richard Q. Williams, Jean-Olivier Plouchart, Scott K. Springer, E. J. Nowak, Ning Lu, Sungjae Lee
Publikováno v:
IEEE Transactions on Electron Devices. 53:2168-2178
The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact model
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3eb1a7f7ab6a579df6b63d107f267842
https://doi.org/10.1109/ted.2006.880165
https://doi.org/10.1109/ted.2006.880165
Autor:
David J. Frank, Kerry Bernstein, Anne E. Gattiker, E. J. Nowak, Norman J. Rohrer, Wilfried Haensch, D. J. Pearson, Sani R. Nassif, Brian L. Ji
Publikováno v:
IBM Journal of Research and Development. 50:433-449
Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-ou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::994f28da458c64a2ac9228acbfa496ff
https://doi.org/10.1147/rd.504.0433
https://doi.org/10.1147/rd.504.0433
Autor:
K. K. Das, Scott Hanson, David Blaauw, Kerry Bernstein, E. J. Nowak, A. Bryant, Bo Zhai, Wilfried Haensch, Leland Chang, Dennis Sylvester
Publikováno v:
IBM Journal of Research and Development. 50:469-490
Energy efficiency has become a ubiquitous design requirement for digital circuits. Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy use. In this work, we review circuit behavior at low voltages, specifically in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2baa85b1e53f1978a377f0f377cce6c6
https://doi.org/10.1147/rd.504.0469
https://doi.org/10.1147/rd.504.0469
Autor:
Xinhui Wang, Arvind Kumar, Wilfried Haensch, Paul M. Solomon, A. Bryant, Massimo V. Fischetti, E. J. Nowak, Omer H. Dokumaci, Jeffrey B. Johnson, Robert H. Dennard
Publikováno v:
IBM Journal of Research and Development. 50:339-361
To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c038b5f727fe6eba64b191eca703c16c
https://doi.org/10.1147/rd.504.0339
https://doi.org/10.1147/rd.504.0339
Autor:
Karthik Balakrishnan, E. J. Nowak, Frederic Allibert, Narasimha Rao Mavilla, Gen Tsutsui, Richard G. Southwick, Terence B. Hook, Xin Sun, Jay W. Strane, Bruce B. Doris, Dechao Guo
Publikováno v:
2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
FinFETs may in principle be built on either bulk [1–3] or SOI [4–5] substrates. In this paper we will review some of the technical issues associated with choice of substrate, directly comparing empirical results on 10nm hardware for which all the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34f414f077a8a606ba3798ea4d6fe195
https://doi.org/10.1109/s3s.2014.7028186
https://doi.org/10.1109/s3s.2014.7028186
Autor:
Patrick W. DeHaven, J. Kuss, Kang-ill Seo, R. Divakaruni, H. He, Reinaldo A. Vega, H. Shang, Theodorus E. Standaert, T. Wu, Darsen D. Lu, Kangguo Cheng, Huiming Bu, Myung-Hee Na, Z. Zhu, Charan V. V. S. Surisetty, James J. Demarest, R. Sampson, T. Hook, Walter Kleemeier, James Chingwei Li, J. Faltermeier, G. Gifford, T. Levin, Ali Khakifirooz, Sebastian Naczas, Henry K. Utomo, Yunpeng Yin, Dinesh Gupta, Ajey Poovannummoottil Jacob, N. Klymko, Anita Madan, Mukesh Khare, Balasubramanian S. Pranatharthi Haran, Soon-Cheon Seo, Ok Injo, D.I. Bae, P. Oldiges, K. Rim, Robin Chao, Bruce B. Doris, D. Song, E. J. Nowak
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive dev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7897b29a2d600d29948210b321a03e10
https://doi.org/10.1109/vlsit.2014.6894390
https://doi.org/10.1109/vlsit.2014.6894390
Publikováno v:
Physics of Semiconductor Devices ISBN: 9783319030012
Recent advances in FinFET technology include fins with tapered sidewalls in addition to conventional vertical sidewall fins. Our 3-D TCAD simulation results suggest that for low to moderately doped fins, vertical sidewall fins have superior electrica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20f3f7c46324041a07108db7a83ffbb3
https://doi.org/10.1007/978-3-319-03002-9_2
https://doi.org/10.1007/978-3-319-03002-9_2
Publikováno v:
Proceedings of the IEEE. 89:259-288
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations en
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c76ff8426d8348daf51fcc5924a738c
https://doi.org/10.1109/5.915374
https://doi.org/10.1109/5.915374
Publikováno v:
IEEE Transactions on Electron Devices. 42:697-703
Self-aligned titanium silicide is often used to minimize the polysilicon and diffusion sheet resistances. Current is delivered to the channel of FET's, the body of diffused resistors, and into the active region of NPN's through the titanium silicide/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d485109ec187ebf7e1fd1ed25f74020
https://doi.org/10.1109/16.372074
https://doi.org/10.1109/16.372074